DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/23/2025; 01/23/2026 are is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,387,672 in view of Bang et al. (US 2021/0183983), further in view of Cao et al. (US 2022/0027004).
Claims 1 and 6 of US Patent ‘672 discloses the limitations of claim 1 of instant application. Claim 1 of US Patent ‘672 does not disclose “the transmissive area configured to transmit an external light; a data line extended in the second direction, disposed in a same direction as the initialization line, in the display area; a planarization layer disposed on the data line and the initialization line; a light emitting diode comprising an anode electrode, an organic light emitting layer and a cathode electrode provided over the planarization layer; a bank layer disposed on the planarization layer and overlapped with the data line; and a black matrix overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area”
Bang et al. discloses the display area including a transmissive area, the transmissive area configured to transmit an external light (fig.1, display area DA2 may include transmissive area TA that may transmit light that may be output by the component to the outside or that may travel from the outside toward the component; para.0071,0082), a data line extended in the second direction, disposed in a same direction as the initialization line, in the display area (fig.3,5B-6; data line DL and initialization line VIL extend in same direction, para.0127,0151); a planarization layer disposed on the data line and the initialization line (fig.8,12; planarization layer 117 disposed on line group VL including data line and initialization line; para.0128,0150-0151,0157); a light emitting diode comprising an anode electrode, an organic light emitting layer and a cathode electrode provided over the planarization layer (fig.8, para.0119,0133,0159; subpixels pa1-pa3, include first pixel electrode 221a-c, emission layer 223a-c, opposite electrode 225a-c); a bank layer disposed on the planarization layer and overlapped with the data line (fig.8, pixel defining layer 119; para.0164); and a black matrix [overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area] (para.0091, black matrix may be arranged or disposed on the display panel).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of US Patent ‘672 with the teachings of Bang et al., the motivation being to provide a display device where the transmissive area may be increased or maximized and a lifespan of a panel may be increased. Accordingly, a highly reliable display device may be provided.
US Patent ‘672 in view of Bang et al. disclose a non transmissive area CA corresponding to pixel areas (Bang-pa1-pa3; fig.5a-5b, 8; para.0123-0127) adjacent a transmissive area TA which transmits light, and where a black matrix may be arranged or disposed on the display panel (para.0091), but do not expressly disclose the black matrix overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area.
Cao et al. discloses where black matrix (123) disposed in non-light transmission region (A2), where a plurality of transistors are disposed in the non-transmission region (para.0039, 0047).
It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device disclosed by US Patent ‘672 in view of Bang et al., with the teachings of Cao et al., the motivation being to block light from adjacent light transmissive region.
Claims 1-16 of US Patent 672 disclose the limitations of claims 2-18 of instant application.
Instant Application: 19/278,694
1. A display device comprising: a substrate provided with a display area on which a plurality of subpixels is disposed, the display area including a transmissive area and a non-transmissive area, the transmissive area configured to transmit an external light, a first non-display area disposed at a first side of the display area and a second non- display area disposed at a second side facing the first side;
US Patent: 12,387,672
1. A transparent display device comprising: a substrate provided with a display area on which a plurality of subpixels is disposed, a first non-display area disposed at a first side of the display area and a second non-display area disposed at a second side facing the first side;
a first common power electrode extended in a first direction in the first non-display area;
a second common power electrode extended in the first direction in the second non- display area, the second common power electrode opposite and facing the first common power electrode;
a first common power electrode extended in a first direction in the first non-display area;
a second common power electrode extended in the first direction in the second non-display area, the second common power electrode opposite and facing the first common power electrode;
an initialization line extended from the first non-display area to the second non-display in a second direction transverse to the first direction, the initialization line spaced apart from the second common power electrode from a plan view, the initialization line electrically coupling the first common power electrode with the second common power electrode;
an initialization line extended from the first non-display area to the second non-display in a second direction transverse to the first direction, the initialization line spaced apart from the second common power electrode from a plan view, the initialization line electrically coupling the first common power electrode with the second common power electrode and supplying an initialization voltage to each of the plurality of subpixels;
a data line extended in the second direction, disposed in a same direction as the initialization line, in the display area;
a connection line of which one end is coupled with the second common power electrode and the other end is coupled with the initialization line;
a planarization layer disposed on the data line and the initialization line;
a light emitting diode comprising an anode electrode, an organic light emitting layer and a cathode electrode provided over the planarization layer;
a first pixel power electrode disposed parallel to the first common power electrode in the first non-display area; a second pixel power electrode disposed parallel to the second common power electrode in the second non-display area; and
a bank layer disposed on the planarization layer and overlapped with the data line; and
a black matrix overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area.
a pixel power line electrically coupled to the first pixel power electrode and the second pixel power electrode, the pixel power line overlapping the first common power electrode in the first non-display area; wherein the second pixel power electrode is disposed on the same layer as the second common power electrode or the initialization line.
6. The transparent display device of claim 1, wherein the pixel power line extended from the display area in the second direction supplies a second power voltage to each of the plurality of subpixels, and wherein the display area includes a non-transmissive area provided with the initialization line and the pixel power line and a transmissive area provided between the initialization line and the pixel power line.
Claim 2
Claim 3
Claim 4
Claim 5
Claim 6
Claim 7
Claim 8
Claim 9
Claim 10
Claim 11
Claim 12
Claim 13
Claim 14
Claim 15
Claim 16
Claim 17
Claim 18
Claim 1
Claim 1
Claim 2
Claim 3
Claim 4
Claim 5
Claim 6
Claim 7
Claim 8
Claim 9
Claim 10
Claim 11
Claim 12
Claim 13
Claim 14
Claim 15
Claim 16
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,4-7,13-14,20,22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2020/0212161) in view of Bang et al. (US 2021/0183983), further in view of Cao et al. (US 2022/0027004)
As to Claim 1, Choi et al. discloses A display device comprising: a substrate provided with a display area on which a plurality of subpixels is disposed (fig.4, display area DA; para.0091-0092), the display area including a transmissive area and a non-transmissive area, the transmissive area configured to transmit an external light, a first non-display area disposed at a first side of the display area (fig.4, lower peripheral area PA (including regions MP1-MP3 ) and a second non- display area disposed at a second side facing the first side (fig.4, upper peripheral area PA (including regions MP4-MP5));
a first common power electrode extended in a first direction in the first non-display area (fig.4, para.0075- conductive pattern 1621 extended in a horizontal direction); a second common power electrode extended in the first direction in the second non- display area, the second common power electrode opposite and facing the first common power electrode (fig.4, conductive pattern 1622 extended in the horizontal direction);
an initialization line extended from the first non-display area to the second non-display in a second direction transverse to the first direction (fig.4, para.0075; initialization line Vint2L extends from pattern region MP3 to region MP4 passing through the display area DA in vertical direction),
the initialization line spaced apart from the second common power electrode from a plan view (fig.4-6, para.0109-0111, initialization line Vint2L is disposed in pattern region MP3 and extend to pattern region MP4, and is spaced apart from conductive pattern 1622 which is disposed in pattern region MP5), the initialization line electrically coupling the first common power electrode with the second common power electrode (fig.4, initialization line Vint2L is electrically connected to conductive pattern 1621 and to conductive pattern 1622; para.0073, 0075,0077, 0109-0111),
a data line extended in the second direction, disposed in a same direction as the initialization line, in the display area (fig.1,4; data lines DL extend in same direction (vertical direction) as initialization)
a planarization layer disposed on the data line and the initialization line (fig.5-6, planarization layer 170 disposed on initialization line (disposed in MP3));
a light emitting diode comprising an anode electrode, an organic light emitting layer and a cathode electrode provided over the planarization layer (fig.5-6; OLED- para.0093);
a bank layer disposed on the planarization layer and overlapped with the data line (fig.5-6, pixel defining layer 180); and
a black matrix overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area.
Choi et al. does not expressly disclose the display area including a transmissive area and a non-transmissive area, the transmissive area configured to transmit an external light, a planarization layer disposed on the data line; a bank layer overlapped with the data line; a black matrix overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area.
Bang et al. discloses a display area including a transmissive area and a non-transmissive area, the transmissive area configured to transmit an external light (fig.1,5; 8; non transmissive area CA and transmissive area TA in display area DA2, where transmissive area may transmit light that may be output by the component to the outside or that may travel from the outside toward the component; para.0071,0082,0123-0127); a planarization layer disposed on the data line (fig.8,12; planarization layer 117 disposed on line group VL including data line and initialization line; para.0128,0150-0151,0157); a bank layer disposed on the planarization layer and overlapped with the data line (fig.8, pixel defining layer 119; para.0164).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Choi et al., with the teachings of Bang et al., the motivation being to provide a display device where the transmissive area may be increased or maximized and a lifespan of a panel may be increased. Accordingly, a highly reliable display device may be provided.
Choi et al in view of Bang et al. disclose a non-transmissive area CA corresponding to pixel areas (Bang-figs.5,8- pixel areas pa1-pa3; para.0123-0127) adjacent a transmissive area TA, and where a black matrix may be arranged or disposed on the display panel (Bang-para.0091), but do not expressly disclose the black matrix overlapped with the bank layer, the data line, and the initialization line in the non-transmissive area beside the transmissive area.
Cao et al. discloses where black matrix (123) disposed in non-light transmission region (A2), where a plurality of transistors are disposed in the non-transmission region (para.0039, 0047).
It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device disclosed by Choi et al. in view of Bang et al., with the teachings of Cao et al., the motivation being to block light from adjacent light transmissive region.
As to Claim 4, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein the initialization line applies an initialization voltage at an initialization period (Choi-fig.3, initialization periods t1-t2, para.0059,0063), and applies a first power voltage at an emission period (Choi-fig.3, emission period t4; para.0063,0059).
As to Claim 5, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein the initialization voltage and the first power voltage have substantially the same voltage (Choi-para.0046- initialization voltage may be the same voltage as ELVSS).
As to Claim 6, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein the initialization line supplies an initialization voltage to a driving transistor of each of the plurality of subpixels at an initialization period (Choi-fig.3-initialization period t1-t2; para.0063).
As to Claim 7, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein the initialization line transfers a first power voltage applied from the first common power electrode to the second common power electrode at an emission period (Choi-fig.3-emission period t4, para.0063,0074-0075,0077) .
As to Claim 13, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein one end of the initialization line is coupled with the first common power electrode (Choi-figs.4-5, initialization lone Vint2L connected to pattern 1621; para.0073).
As to Claim 14, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein the initialization line and the second common power electrode are disposed to be spaced apart from each other on the same layer (Choi-fig.5-6; initialization Vint2L disposed in pattern region MP3 and conductive pattern 1622 in MP5).
As to Claim 20, Choi et al. in view of Bang et al., as modified by Cao et al. disclose n encapsulation layer disposed on the cathode electrode (Choi-fig.5-6, encapsulation 300, cathode 230; para.0098).
As to Claim 22, Choi et al. in view of Bang et al., as modified by Cao et al. disclose wherein the cathode electrode overlaps the initialization line in the second non-display area (Choi-fig.6, cathode 230, vint2L disposed in pattern region MP4)
As to Claim 23, Choi et al. in view of Bang et al. as modified by Cao et al. disclose wherein the cathode electrode overlaps the second common power electrode in the second non-display area (Choi-fig.6, cathode 230 overlaps conductive pattern 1622; Bang-fig.8, opposite electrode 225 overlap signal line group VL; para.0106,0214).
Claim(s) 2, 10-12,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2020/0212161) in view of Bang et al. (US 2021/0183983), further in view of Cao et al. (US 2022/0027004), and of Lee et al. (US 2021/0328002).
As to Claim 2, Choi et al. in view of Bang et al., as modified by Cao et al. do not expressly disclose, but Lee et al. discloses: a connection line of which one end is coupled with the second common power electrode and the other end is coupled with the initialization line (fig.2, common voltage line VSL, one end connected to common voltage ELVSS and another end to initialization line VL1, VL2; para.0061,0065,0067,0100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Choi et al. in view of Bang et al., as modified by Cao et al., with the teachings of Lee et al., such that a one end of the common voltage line (connection line) is connected to conductive pattern 1622 one end to initialization voltage line. The motivation being so that a low common voltage is thereby provided as an initialization voltage.
As to Claim 10, Choi et al. in view of Bang et al., as modified by Cao et al., disclose a driving transistor comprised of an active layer (Choi-fig.2,5; para.0091; driving transistor DT; semiconductor layer 120), a gate electrode (Choi-fig.2,5; gate electrode 140; para.0089), a source electrode (Choi-fig.2,5; source electrode 161s; para.0089), and a drain electrode (Choi-fig.2,5; drain electrode 161d; para.0089); wherein the planarization layer includes a first planarization layer and a second planarization layer (Choi-fig.5, planarization layer 170), wherein the first planarization layer provided over the driving transistor (Choi-fig.5, planarization layer 170; para.0090); an anode auxiliary electrode is provided over the first planarization layer; wherein the second planarization layer provided over the anode auxiliary electrode; wherein the light emitting diode is provided over the second planarization layer (Choi-fig.5, OLED (including layers 210,120,230)), and wherein the initialization line is provided on the same layer as the anode auxiliary electrode (Bang-fig.8, connecting electrode CW and line group VL disposed on same layer 115).
Choi et al. in view of Bang et al., as modified by Cao et al., do not expressly disclose, but Lee et al. discloses: an anode auxiliary electrode is provided over the first planarization layer (Lee-fig.4-5; para.0110; connecting electrode 191 is connected to pixel electrode (anode) 210); wherein the second planarization layer provided over the anode auxiliary electrode (fig.4-5, para.0115, second planarization layer 117 over connecting electrode 191).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Choi et al. in view of Bang et al., as modified by Cao et al., with the teachings of Lee et al., to provide electrical connection between the organic light emitting device and the other elements of the device.
As to Claim 11, Choi et al. in view of Bang et al., as modified by Cao et al. and Lee et al. disclose plurality of signal lines extended from the same layer as the source electrode and the drain electrode in the second direction (Choi-para.0102, signal lines may be formed same layer as source/drain electrodes 161s/161d; Bang-fig.4).
As to Claim 12 Choi et al. in view of Bang et al., as modified by Cao et al. and Lee et al. disclose wherein the initialization line has a width wider than a width of each of the plurality of signal lines (Lee- as depicted in fig.4-5, width of initialization line VL1, VL2 is wider than width of data line DL1p (DL1), DL2, power line PL1b, scan line SL).
As to Claim 19, Choi et al. in view of Bang et al., as modified by Cao et al. disclose a color filter may be disposed on the display panel (Bang-para.0091).
Choi et al. in view of Bang et al., as modified by Cao et al. do not expressly disclose, but Lee et al. discloses: a color filter layer disposed to correspond to the light emitting diode (fig.13, filters 520,540,560 correspond to OELD1-OLED3 respectively).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Choi et al. in view of Bang et al., as modified by Cao et al., with the teachings of Lee et al., to display a color of the respective OLED.
Allowable Subject Matter
Claim 3,8-9,15, 16-18,21,24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the double patenting rejections as set forth above.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “a first pixel power electrode disposed along a same direction as the first common power electrode in the first non-display area; a second pixel power electrode disposed along a same direction as the second common power electrode in the second non-display area; and a pixel power line electrically coupled to the first pixel power electrode and the second pixel power electrode, the pixel power line overlapping the first common power electrode in the first non-display area; wherein the second pixel power electrode is disposed on the same layer as the second common power electrode or the initialization line” along with the other limitations in the claim.
Claim 15 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “…wherein the connection line is disposed on a different layer than the initialization line and the second common power electrode” along with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 form.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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