Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 24 July 2025 for application number 19/278,788. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 25 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 24 February 2025 (KR10-2025-0023508).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 24 July 2025 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Construction
The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II). See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Note that the limitations “when the flag is in a second state, reading, by the memory controller, first read data from the storage medium and outputting, by the memory controller, the first read data as read data corresponding to the first read command” (in claim 19) may never be reached within the scope of the claim under the broadest reasonable interpretation since it may occur that the flag is not in a second state and the “when” condition may never be met; and “when a plurality of read commands, each of which includes a read address at least partially matching the write address, are sequentially received and held pending, storing, by the memory controller, the plurality of read commands as a linked list in the read ready queue” (in claim 22) may never be reached within the scope of the claim under the broadest reasonable interpretation since it may occur that a plurality of read command are not sequentially received and held pending, and storing them as a linked list in the read ready queue and the “when” condition may never be met. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II). Examiner is applying the present prior to read on both claims as the prior art efficiently reads on the limitations that are definitive and not dependent on “when” or if a condition is met.
It is suggested method claims 19 and 22 be amended where the limitation is definitively established the flag as being in the second state (for claim 19), and the limitations of the plurality of read commands existing along with the remaining limitations (for claim 22). Claims 23 – 25 depend from claim 22 and further limit the contingent limitation, therefore they are also contingent and are not included in the broadest reasonable interpretation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, 17, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Fux et al. [hereafter as Fux], US Pub. No. 2024/0045594 A1 in view of Davis et al. [hereafter as Davis], US Patent No. 6,021,473.
As per claim 1, Fux discloses a data storage apparatus comprising:
a storage medium [“In embodiments of the present invention, a memory controller interacts with a memory device to perform read and write operations where the memory device is organized in multiple independently accessible memory banks.”] [para. 0023]; and
a memory controller [“In embodiments of the present invention, a memory controller interacts with a memory device to perform read and write operations where the memory device is organized in multiple independently accessible memory banks.”] [para. 0023] configured to:
determine, when a read address of a first read command to be performed at least partially matches a write address of a first write command being currently executed, whether to pend the first read command based on the first write command [“The write staging buffer 34 performs address matching to determine if the read address of an incoming read request matches any of the memory addresses of the pending write requests... Following the pending write request being evicted, the read ingress buffer 32 transfers the read request having the matching address to the read queue 36.”] [para. 0056],
store the pending first read command in a read ready queue [“…the read ingress buffer 32 transfers the read request having the matching address to the read queue 36.”] [para. 0056], and
process a command queued in the read ready queue after execution of the first write command is completed [“The read queue 130 and write queue 132 determine which of the active requests stored therein are eligible to be executed at the memory device. The read queue 130 and write queue 132 always try to send all eligible commands to the command selector 135. The command selector 135 arbitrates the commands using the predefined priority rules and selects a winning command at each clock cycle (or each x number of clock cycles).”] [para. 0086].
However, Fux does not explicitly disclose a flag set corresponding to the write command,
wherein the flag is configured to indicate that first write data associated with the first write command is flushed from a buffer memory device to the storage medium or remains in the buffer memory device.
Davis teaches a flag set corresponding to the write command [“Status bits 223 are additional bits provided in memory of CPU-PCI bridge 204 for data locations 230 in the write buffer 220. When a data item is stored in a particular data location 230 in the write buffer 220, a status bit 223 that is associated with the particular location is set (e.g., to a "1" value) to indicate that the data location is storing a data item. When the write buffer is flushed, as described below, the status bits 223 are cleared. The status bits may be set or cleared using control lines 229.”] [col. 7, lines 15-23],
wherein the flag is configured to indicate that first write data associated with the first write command is flushed from a buffer memory device to the storage medium or remains in the buffer memory device [“Status bits 223 are additional bits provided in memory of CPU-PCI bridge 204 for data locations 230 in the write buffer 220. When a data item is stored in a particular data location 230 in the write buffer 220, a status bit 223 that is associated with the particular location is set (e.g., to a "1" value) to indicate that the data location is storing a data item. When the write buffer is flushed, as described below, the status bits 223 are cleared. The status bits may be set or cleared using control lines 229.”] [col. 7, lines 15-23].
Fux and Davis are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Fux with Davis in order to modify Fux where “a flag set corresponding to the write command,
wherein the flag is configured to indicate that first write data associated with the first write command is flushed from a buffer memory device to the storage medium or remains in the buffer memory device” as taught by Davis. One of ordinary skill in the art would be motivated to combine Fux with Davis before the effective filing date of the claimed invention to improve a system that “maintains coherency of written data items in an efficient manner… the write buffer is not needlessly flushed”. [Davis, col. 4, last paragraph].
Claim 17 is rejected with like reasoning.
Claim 10 is rejected with like reasoning as claims 1 and 17 above, except for the following remaining claims limitations:
receive a first write command, a first write address and first write data,
store the first write data in a buffer memory device to set a flag to a first state,
transmit the first write data from the buffer memory device to a storage medium to set the flag to a second state.
Davis teaches receive a first write command, a first write address and first write data [“Status bits 223 are additional bits provided in memory of CPU-PCI bridge 204 for data locations 230 in the write buffer 220. When a data item is stored in a particular data location 230 in the write buffer 220...”] [col. 7, lines 15-23],
store the first write data in a buffer memory device to set a flag to a first state [“…a data item is stored in a particular data location 230 in the write buffer 220, a status bit 223 that is associated with the particular location is set (e.g., to a "1" value) to indicate that the data location is storing a data item...”] [col. 7, lines 15-23],
transmit the first write data from the buffer memory device to a storage medium to set the flag to a second state [Examiner is interpreting the status bit being cleared as a second state] [“… a status bit 223 that is associated with the particular location is set (e.g., to a "1" value) to indicate that the data location is storing a data item. When the write buffer is flushed, as described below, the status bits 223 are cleared. The status bits may be set or cleared using control lines 229.”] [col. 7, lines 15-23].
As per claim 19, Fux in view of Davis teaches the method of claim 17, Davis teaches further comprising, when the flag is in a second state, reading, by the memory controller, first read data from the storage medium and outputting, by the memory controller, the first read data as read data corresponding to the first read command [Contingent limitation as stated above in Claim Construction],
wherein the flag in the second state is configured to indicate a status that the first write data is flushed from the buffer memory device to the storage medium [“Status bits 223 are additional bits provided in memory of CPU-PCI bridge 204 for data locations 230 in the write buffer 220. When a data item is stored in a particular data location 230 in the write buffer 220, a status bit 223 that is associated with the particular location is set (e.g., to a "1" value) to indicate that the data location is storing a data item. When the write buffer is flushed, as described below, the status bits 223 are cleared. The status bits may be set or cleared using control lines 229.”] [col. 7, lines 15-23].
As per claim 22, Fux in view of Davis teaches the method of claim 17, Fux discloses further comprising, when a plurality of read commands, each of which includes a read address at least partially matching the write address, are sequentially received and held pending, storing, by the memory controller, the plurality of read commands as a linked list in the read ready queue [Contingent limitation as stated above in Claim Construction] [“The write staging buffer 34 performs address matching to determine if the read address of an incoming read request matches any of the memory addresses of the pending write requests... Following the pending write request being evicted, the read ingress buffer 32 transfers the read request having the matching address to the read queue 36.”] [para. 0056].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 25 have received a first action on the merits and are subject of a first action non-final. Claims 1, 10, 17, 19, and 22 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 2, 3, 4, 6, 11, 12, 13, 15, 18, and 20 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims in independent form. Claims 5, 7 – 9, 14, 16, and 21 depend from claims 4, 6, 13, 15, and 20 and are objected to as considered containing allowable subject matter based upon their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 2, 11, 18 the prior art of record, neither anticipates, nor renders obvious a memory controller that reads a first write data from a buffer memory device and output the first write data as read data that corresponds to a first read command based on a set flag being in a first state.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 3 and 12 the prior art of record, neither anticipates, nor renders obvious memory controller that reads first read data from a storage medium and output the first read data as read data that corresponds to a first read command based on a set flag being in a second state.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 4, 13, and 20 the prior art of record, neither anticipates, nor renders obvious a memory controller that allocates an index to a pending first read command and stores the pending first read command in the allocated index region of a read ready queue. Claims 5, 14, and 21 depend from claims 4, 13, and 20 and would be allowable.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 6 and 15 the prior art of record, neither anticipates, nor renders obvious multiple read commands with a respective read address that at least partially matches a write address, and are sequentially received and held pending in a read ready queue, where they are stored as a linked list by the memory controller. Claim 7 – 9 and 16 depend from claims 6 and 15 and would be allowable based on their dependency.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sambangi et al., US Patent No. 12,265,729 B1 – teaches [“For example, one or more bits of write buffer status register 424 may indicate a type of flush operation that is being performed at write buffer 426.”] [col. 17, lines 28-30] [“For example, memory controller 422 may be configured to implement one or more registers, such as write buffer status register 424, which is configured to store status information related to write buffer 426. To illustrate, the write buffer status register 424 may indicate whether the write buffer is full, performing a flush operation, prioritizing a flush operation, etc.”] [col. 14, lines 26-32].
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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