DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-8 and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al, US Pub. 2019/0213459.
The applied reference has a common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claims 1, 8, and 19, Kim et al disclose a mode power changing and a smart card comprising: a smart card 100 having an antenna 110; a rectifier 120, a regulator converter 130, a voltage regulator 140, a clamp circuit 150, a load modulator 160, and a regulator controller 170; the antenna 110 may transmit or receive a radio frequency signal to communicate with a card reader; the antenna 110 may have an inductor L and a capacitor C connected to each other in parallel; the antenna 110 may convert the radio frequency signal transmitted from the card reader into an electrical signal through electromagnetic induction of the inductor L and the capacitor C; the antenna 110 may have a loop antenna structure to communicate with the card reader; the antenna 110 may have a dual resonance loop structure for a high electromagnetic efficiency; the rectifier 120 may include rectifier circuits, e.g., a half-wave rectifier circuit and a full-wave rectifier circuit (having 4 diodes); the regulator converter 130 may control an operation mode of the voltage regulator 140 such that the voltage regulator 140 may operate in one of a first regulator mode and a second regulator mode according to a mode selection signal Mode SEL; the power supply circuit of the smart card 100 may include the antenna 110, the rectifier 120, the regulator converter 130, the voltage regulator 140, and the clamp circuit 150; the variable resistor VR may include a first resistor R1, a second resistor R2, and a modulation switch SWO; the first resistor R1, the modulation switch SWO, and second resister R2 may be connected in series, and the first and second resistors R1 and R2 are connected to the both ends of the antenna 110, respectively. (See fig. 1-2; par. 0024-0040).
Regarding claim 2, wherein the first diode is a diode-connected first transistor; and the second diode is a diode-connected second transistor (see Fig. 2, element 120).
Regarding claim 7, wherein the voltage regulator is further configured to amplify a difference between a voltage corresponding to the voltage of the first node and a desired reference voltage (see par. 0029+).
Regarding claim 20, wherein the first transistor is connected between the output terminal of the rectifier and a second node; the second transistor is connected between the second node and the first node; the first transistor is configured to be in an on-state during a second mode of the smart card, the second mode being a mode during which the load of the load circuit is not modulated; and the second transistor is configured to control a voltage of the second node during the second mode. (See Fig. 2, par. 0034-0040).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,393,820 (hereinafter ‘820 Patent). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claimed invention is a broader recitation of the ‘820 Patent. For instance in claim 1 of the current application and in the ‘820 Patent, the applicant claims:
Application No. 19/278,915
Patent No. 12,393,820
A smart card comprising: an antenna configured to receive at least one radio signal; a load circuit that is connected to both ends of the antenna; a rectifier configured to rectify the at least one radio signal received through the antenna, and provide the rectified signal to an output terminal; and a power generator including a voltage regulator, a first diode, and a second diode, the voltage regulator configured to provide an internal voltage, the first diode and the second diode connected in series between the output terminal of the rectifier and a first node, and the first node is configured to receive the internal voltage during a first mode of the smart card, the first mode being a mode during which a load of the load circuit is modulated, wherein, in the first mode, depending on load modulation by the load circuit, a rectified voltage of the rectified signal is either a level of the internal voltage or a sum level of the internal voltage and threshold voltages of the first and second diodes.
A smart card comprising: an antenna configured to receive at least one radio signal; a load circuit that is connected to both ends of the antenna; a rectifier configured to rectify the at least one radio signal received through the antenna, and provide the rectified signal to an output terminal; and a power generator including a voltage regulator, a first diode, and a second diode, the voltage regulator configured to provide an internal voltage, the first diode and the second diode connected in series between the output terminal of the rectifier and a first node, and the first node is configured to receive the internal voltage during a first mode of the smart card, the first mode being a mode during which a load of the load circuit is modulated, wherein the internal voltage is supplied to at least one processor configured to control the smart card, the load circuit comprises a first resistor, a modulation switch, and a second resistor connected to the both ends of the antenna, in response to the modulation switch being on, a rectified voltage follows the internal voltage, the rectified voltage being a voltage of the output terminal of the rectifier, and in response to the modulation switch being off, the rectified voltage follows a voltage obtained based on a threshold voltage of the first diode, a threshold voltage of the second diode, and the internal voltage.
Thus, in respect to above discussions, it would have been obvious to an artisan at the time the invention was made to use the teaching of claims 1-20 of the ‘820 Patent as a general teaching for a smart card, to perform the same function as claimed in the present invention. The instant claims obviously encompass the claimed invention of the ‘820 Patent and differ only in terminology. The extent that the instant claims are broaden and therefore generic to claimed invention of ‘820 Patent [species], In re Goodman 29 USPQ 2d 2010 CAFC 1993, states that a generic claim cannot be issued without a terminal disclaimer, if a species claim has been previously been claimed in a co-pending application.
The obviousness-type double patenting rejection is a judicially established doctrine based upon public policy and is primarily intended to prevent prolongation of the patent term by prohibiting claims in a second patent not patentably distinct from the claims in a first paten. IN re Vogel, 164 USPQ 619 (CCPA 1970). A timely filed terminal disclaimer in compliance with 37 C.F.R. & 1.321(b) would overcome an actual or provisional rejection on this ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 C>FR> &1.78(d).
Allowable Subject Matter
Claims 3-6 and 9-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon filing of a terminal disclaimer.
The following is a statement of reasons for the indication of allowable subject matter: The applicant teaches a smart card which includes an antenna connected to a load circuit, a rectifier for rectifying the at least one radio signal received through the antenna, a power generator including a voltage regulator, a first and second diodes, a first node for receiving the internal voltage during a first mode of the smart card, wherein, in the first mode, depending on load modulation by the load circuit, a rectified voltage of the rectified signal is either a level of the internal voltage or a sum level of the internal voltage and threshold voltages of the first and second diodes, wherein the first transistor is connected between the output terminal of the rectifier and a second node; the second transistor is connected between the second node and the first node; the first transistor is configured to be in an on-state during a second mode of the smart card, the second mode being a mode during which the load of the load circuit is not modulated; and the second transistor is configured to control a voltage of the second node during the second mode, or wherein the load circuit comprises a first resistor, a modulation switch, and a second resistor connected to the both ends of the antenna; in response to the modulation switch being on, a rectified voltage follows the internal voltage, the rectified voltage being a voltage of the output terminal of the rectifier; and in response to the modulation switch being off, the rectified voltage follows a voltage obtained based on the threshold voltage of the first diode, the threshold voltage of the second diode, and the internal voltage. These limitations in conjunction with other limitations in the claims were not shown by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL ST CYR whose telephone number is (571)272-2407. The examiner can normally be reached M to F 8:00-8:00.
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DANIEL ST CYR
Primary Examiner
Art Unit 2876
/DANIEL ST CYR/Primary Examiner, Art Unit 2876