DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the Continuation filed on 07/04/2025
This is a CON of 18/295,277 now a PAT 12,420,499 B2
Application claims a FP date of Apr 15, 2022
Claims 1-23 are canceled
Claim 24 is independent
Claims 24-36 are pending
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/11/2025 and 05/19/2026 are in compliance with the provisions of 37 CFR 1.97 and 37 CFR 1.98(a)(4). Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in the instant Application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 24-36 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12,402,499 B2. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the following table.
24. Application: A semiconductor device including an element substrate having a main surface provided with
1. Patent 12,402,499 B2: a semiconductor device including an element substrate having a main surface provided with
(a) a pixel region where a plurality of pixels are arranged and
1. Patent 12,402,499 B2: (a) a pixel region where a plurality of pixels are arranged and
(b) a peripheral region where an alignment mark and a plurality of terminals are arranged, the device comprising:
1. Patent 12,402,499 B2: (b) a peripheral region where an alignment mark and a plurality of terminals are arranged, the device comprising:
an interlayer insulating layer arranged in the pixel region and the peripheral region; and
1. Patent 12,402,499 B2: an interlayer insulating layer arranged in the pixel region and the peripheral region;
a transparent insulating layer configured to cover the alignment mark and not to cover the plurality of terminals and each portion between the plurality of terminals,
1. Patent 12,402,499 B2: a transparent insulating layer configured to cover the alignment mark and not to cover the plurality of terminals and each portion between the plurality of terminals,
wherein the alignment mark and the plurality of terminals are arranged over and in contact with the interlayer insulating layer.
1. Patent 12,402,499 B2: wherein the alignment mark and the plurality of terminals are arranged over and in contact with the interlayer insulating layer.
25. Application: wherein the transparent insulating layer further covers the plurality of pixels.
2. Patent 12,402,499 B2: wherein the transparent insulating layer further covers the plurality of pixels.
26. Application: further comprising a plurality of sealing layers configured to cover the plurality of pixels, wherein the transparent insulating layer forms one of the plurality of sealing layers.
3. Patent 12,402,499 B2: further comprising a plurality of sealing layers configured to cover the plurality of pixels, wherein the transparent insulating layer forms one of the plurality of sealing layers.
27. Application: wherein the transparent insulating layer is made of an inorganic material.
4. Patent 12,402,499 B2: wherein the transparent insulating layer is made of an inorganic material.
28. Application: further comprising a color filter layer configured to cover the plurality of pixels, wherein the transparent insulating layer is arranged between the plurality of pixels and the color filter layer.
5. Patent 12,402,499 B2: further comprising a color filter layer configured to cover the plurality of pixels, wherein the transparent insulating layer is arranged between the plurality of pixels and the color filter layer.
29. Application: wherein the transparent insulating layer is made of a resin material.
6. Patent 12,402,499 B2: wherein the transparent insulating layer is made of a resin material.
30. Application: wherein each of the plurality of pixels includes a light emitting element.
7. Patent 12,402,499 B2: wherein each of the plurality of pixels includes a light emitting element.
Claims 31-36 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12,402,499 B2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 24-27 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Takazawa et al. (U.S. Patent Publication 2015/0348914 A1).
Regarding Claim 24, Takazawa discloses a semiconductor device (Figs 1-4, Takazawa discloses an image pickup apparatus/solid-state image pickup element 3) including an element substrate having a main surface (Fig 2A- substrate 11 and 12) provided with (a) a pixel region (Fig 2A – photodetector region 1) where a plurality of pixels are arranged and (b) a peripheral region (Fig 2 discloses the region around the circuit area 203 - interpreted as a peripheral region) where an alignment mark (Fig 2A- alignment mark 14) and a plurality of terminals (Fig 2A-3B and in ¶0094, ¶0101 Takazawa discloses about bonding electrodes 12a which has been interpreted as “terminals”) are arranged (In Figs 1,2 and in Col 2, lines 35-40, Yang discloses plurality of electrode terminals 110),
the device comprising:
an interlayer insulating (¶0073 interlayer oxide film 18) arranged in the pixel region and the peripheral region (Fig 3B discloses the interlayer oxide film 18); and
a transparent insulating layer (In ¶0065; light-transmitting region T1 as shown in Fig 3A) configured to cover the alignment mark (In ¶0065, Takazawa discloses that the upper side of the alignment mark 14 is covered by light-transmitting region T1 as shown in Fig 3A.) and not to cover the plurality of terminals and each portion between the plurality of terminals (Takazawa in ¶0073 discloses that the interlayer oxide film 18 is interposed between the light-shielding layer 15 and the alignment mark 14 – and therefore does not cover the bonding electrodes 12a),
wherein the alignment mark (Fig 1 – alignment mark 112; Fig 4 - 202) and the plurality of terminals (plurality of electrode terminals 110) are arranged over and in contact with the insulating layer (It is clearly disclosed in Fig 3B that the alignment mark).
Regarding Claim 25, Takazawa discloses wherein the transparent insulating layer further covers the plurality of pixels (In ¶0073 Takazawa discloses that the Fig 3B discloses the interlayer oxide film 18 transmits detection beam– which essentially discloses it to be “transparent” and Fig 3B also discloses it to cover the pixel portion too).
Regarding Claim 26, Takazawa discloses further comprising a plurality of sealing layers configured to cover the plurality of pixels (Fig 2C- bonding layer 13, adhesive layer 13a), wherein the transparent insulating layer (Fig 3B discloses the interlayer oxide film 18) forms one of the plurality of sealing layers (According to Fig 3B – the oxide layer 18 is in the bonding portion 13; ¶0146).
Regarding Claim 27, Takazawa discloses wherein the transparent insulating layer is made of an inorganic material (Fig 3B discloses the insulating layer as interlayer oxide film 18 which is inorganic).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Takazawa et al. (U.S. Patent Publication 2015/0348914 A1) in view of Hori (U.S. Patent Publication Number 2017/0345863 A1).
Regarding Claim 28, Takazawa fails to clearly discloses further comprising a color filter layer configured to cover the plurality of pixels, wherein the transparent insulating layer is arranged between the plurality of pixels and the color filter layer.
Instead in a similar endeavor, Hori discloses further comprising a color filter layer (Fig 18 - layer CF) configured to cover the plurality of pixels (Fig 18 teaches that the color filters cover the plurality of pixels), wherein the transparent insulating layer (Fig 18 – IL1) is arranged between the plurality of pixels (Fig 18 – photodiode - PD) and the color filter layer (Fig 18 - layer CF; Fig 18 clearly discloses that the ).
Takazawa and Hori are combinable because both are related to semiconductor imaging devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the insulating layer as taught by Hori in the imaging module disclosed by Takazawa.
The suggestion/motivation for doing so would have been to electrically isolate the plurality of pixels as disclosed by Hori throughout his disclosure.
Therefore, it would have been obvious to combine Takazawa and Hori to obtain the invention as specified in claim 28.
Regarding Claim 29, Takazawa in view of Hori discloses wherein the transparent layer is made of a resin material (Takasawa: in ¶0080 discloses that the insulating layer is formed of silicon oxide film or the like) It would have been obvious to one having ordinary skill in the art at the time the invention was filed to make the transparent insulating layer of a resin material, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claims 30-33 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Takazawa et al. (U.S. Patent Publication 2015/0348914 A1) in view of Akimoto (U.S. Patent Publication Number 2022/0131027 A1).
Regarding Claim 30, Takazawa fails to clearly disclose wherein each of a plurality of pixels includes a light emitting element.
Instead in a similar endeavor Akimoto discloses wherein each of a plurality of pixels includes a light emitting element (Akimoto’s disclosure is about method for manufacturing image display devices comprising light emitting layer).
Takazawa and Akimoto are combinable because both are related to semiconductor devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use light emitting elements as taught by Akimoto in the module disclosed by Takazawa.
The suggestion/motivation for doing so would have been to manufacture a image display device.
Therefore, it would have been obvious to combine Takazawa and Akimoto to obtain the invention as specified in claim 30.
Regarding Claim 31, Takazawa in view of Akimoto discloses a display device comprising an active element connected to the light emitting device (Akimoto: Akimoto’s disclosure is about method for manufacturing image display devices comprising light emitting layer. In Figs 2-5 and throughout, especially in ¶0082 Akimoto teaches that the light emitting element 150 and the circuit 101 can be electrically connected. Further in ¶0131, Akimoto teaches that the light emitting element 22 is connected in series with a drive transistor 26.).
Regarding Claim 32, Takazawa in view of Akimoto discloses a photoelectric conversion device comprising an optical unit including a plurality of lenses (Takazawa: photoelectric conversion region 1), an image sensor (Takazawa: Fig 1- image sensor 3) configured to receive light having passed through the optical unit (Takazawa: Fig 1- lens unit 1), and a display unit configured to display an image (Akimoto: Fig 28 – image display 601; Takazawa: Fig 1- display 9)), wherein the display unit displays an image captured by the image sensor (Takazawa: ¶0039).
Regarding Claim 33, Takazawa in view of Akimoto discloses a housing provided with a display unit, and a communication unit provided in the housing and configured to perform external communication (Akimoto: Akimoto teaches this in Fig 27 and in the fifth embodiment where he teaches the image display device 501 and a controller 570 which receives input of control signals and in ¶0340 teaches the circuitry for connecting with external terminals).
Regarding Claim 36, Takazawa in view of Akimoto discloses a transistor arranged in the pixel region (Akimoto: Fig 1- transistors 103, 130), wherein the interlayer insulating layer is provided over the transistor (Akimoto: Fig 1- inter-layer insulating film 112).
Claims 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Takazawa et al. (U.S. Patent Publication 2015/0348914 A1) in view of Akimoto (U.S. Patent Publication Number 2022/0131027 A1) and further in view of Oshige (U.S. Patent Publication Number 2021/0066420 A1)
Regarding Claim 34, Takazawa in view of Akimoto fails to disclose an illumination device comprising a light source and at least one light diffusing unit and an optical film.
Instead in a similar endeavor Oshige discloses an illumination device (light source 1402) comprising a light source and at least one light diffusing unit (light diffusion unit 1405) and an optical film (optical filter 1404; also See ¶0148 and Fig 10A).
Takazawa, Akimoto and Oshige are combinable because all are related to semiconductor devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use diffusion plates as taught by Oshige with the light emitting elements as taught by Akimoto in the module disclosed by Takazawa.
The suggestion/motivation for doing so would have been to effectively diffuse light as taught by Oshige in ¶0148.
Therefore, it would have been obvious to combine Takazawa and Akimoto and Oshige to obtain the invention as specified in claim 34.
Regarding Claim 35, Takazawa in view of Akimoto and Oshige discloses a moving body comprising a main body, and a lighting appliance provided in the main body (See ¶0151 and Fig 10B).
Reference Cited
The following prior art made of record but not relied upon is considered pertinent to applicant's disclosure.
Iwamoto et al. ( WO 2021053932; U.S. Patent Publication Number 2023/0024469 A1) discloses a semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.
Kim et al. (U.S. Patent Number 11,423,827 B2) discloses a display device includes: a substrate including a display region including a plurality of pixel regions, and a non-display region at a periphery of the display region; a pixel circuit layer including a plurality of circuit elements in the display region; a display element layer including a plurality of light emitting devices in the display region on the pixel circuit layer; and first and second alignment lines in the non-display region, the first and second alignment lines each having a multi-layered structure. Each of the first and second alignment lines includes: a main line in a same layer as at least one electrode in the display element layer; and at least one sub-line electrically connected to the main line, the at least one sub-line in a same layer as at least one electrode in the pixel circuit layer.
Conclusion
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/PADMA HALIYUR/Primary Examiner, Art Unit 2639 October 7, 2026
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