DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 2 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,407,338 (hereafter ‘338). This is a statutory double patenting rejection.
Claim 2 (with the limitations of parent claim 1) of the instant application recites the same limitations as claim 1 of ‘338. The naming of the capacitors differ in the following manner:
Claim 2 of the instant application
Claim 1 of ‘338
a first capacitor having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together, and a second terminal electrically coupled to the non-inverting input node
a fifth capacitor having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together, and a second terminal electrically coupled to the non-inverting input node
a second capacitor having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together, and a second terminal electrically coupled to the inverting input node
a sixth capacitor having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together, and a second terminal electrically coupled to the inverting input node
a third capacitor having first and second terminals electrically coupled to a gate of the first transistor and an inverting input node of the frequency multiplier, respectively
a first capacitor having first and second terminals electrically coupled to a gate of the first transistor and an inverting input node of the frequency multiplier, respectively
a fourth capacitor having first and second terminals electrically coupled to a gate of the second transistor and a non-inverting input node of the frequency multiplier, respectively
a second capacitor having first and second terminals electrically coupled to a gate of the second transistor and a non-inverting input node of the frequency multiplier, respectively
a fifth capacitor having first and second terminals electrically coupled to a gate of the third transistor and the inverting input node, respectively
a third capacitor having first and second terminals electrically coupled to a gate of the third transistor and the inverting input node, respectively
a sixth capacitor having first and second terminals electrically coupled to a gate of the fourth transistor and the non-inverting input node, respectively
a fourth capacitor having first and second terminals electrically coupled to a gate of the fourth transistor and the non-inverting input node, respectively
However, the structure of the capacitors are the same and therefore, claim 2 of the instant application claims the same invention as claim 1 of ‘338.
Claims 4-6 are rejected merely for being dependent on claim 2.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-9, 14, 16 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2-8 and 16-18 of ‘338. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘338 anticipate the limitations of the claims in the instant application. Differences in the claims are highlighted below. Identical claims are only listed as the claim number.
Claims in the instant application
Claims in ‘338
Claim 1: A frequency multiplier, comprising:
a first transistor having a drain electrically coupled to a non-inverting output node of the frequency multiplier;
a second transistor having a drain electrically coupled to the drain of the first transistor and to the non-inverting output node;
a third transistor having a drain electrically coupled to an inverting output node of the frequency multiplier, and a source electrically coupled to a source of the first transistor;
a fourth transistor having a drain electrically coupled to the drain of the third transistor and to the inverting output node, and a source electrically coupled to a source of the second transistor;
a first capacitor having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together, and a second terminal electrically coupled to the non-inverting input node; and
a second capacitor having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together, and a second terminal electrically coupled to the inverting input node.
Claim 1: A frequency multiplier, comprising:
a first transistor having a drain electrically coupled to a non-inverting output node of the frequency multiplier;
a second transistor having a drain electrically coupled to the drain of the first transistor and to the non-inverting output node;
a third transistor having a drain electrically coupled to an inverting output node of the frequency multiplier, and a source electrically coupled to a source of the first transistor;
a fourth transistor having a drain electrically coupled to the drain of the third transistor and to the inverting output node, and a source electrically coupled to a source of the second transistor;
a first capacitor having first and second terminals electrically coupled to a gate of the first transistor and an inverting input node of the frequency multiplier, respectively;
a second capacitor having first and second terminals electrically coupled to a gate of the second transistor and a non-inverting input node of the frequency multiplier, respectively;
a third capacitor having first and second terminals electrically coupled to a gate of the third transistor and the inverting input node, respectively;
a fourth capacitor having first and second terminals electrically coupled to a gate of the fourth transistor and the non-inverting input node, respectively;
a fifth capacitor having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together, and a second terminal electrically coupled to the non-inverting input node; and
a sixth capacitor having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together, and a second terminal electrically coupled to the inverting input node.
Claim 3
Claim 2
Claim 4
Claim 3
Claim 5
Claim 4
Claim 6
Claim 5
Claim 7
Claim 6
Claim 8
Claim 7
Claim 9
Claim 8
Claim 14: A frequency multiplier, comprising:
a first totem pole arrangement of a first NMOS transistor and a first PMOS transistor having source terminals electrically connected together at a first source node;
a second totem pole arrangement of a second NMOS transistor and a second PMOS transistor having source terminals electrically connected together at a second source node;
a first input terminal capacitively coupled to the first source node;
a second input terminal capacitively coupled to the second source node;
a first capacitor having a first terminal electrically connected to the first source node and a second terminal electrically connected to the first input terminal; and
a second capacitor having a first terminal electrically connected to the second source node and a second terminal electrically connected to the second input terminal; and
wherein each of the first NMOS transistor and the first PMOS transistor has a respective gate terminal electrically connected to the second terminal of the second capacitor and each of the second NMOS transistor and the second PMOS transistor has a respective gate terminal electrically connected to the second terminal of the first capacitor.
Claim 16: A frequency multiplier, comprising:
a first totem pole arrangement of a first NMOS transistor and a first PMOS transistor having source terminals electrically connected together at a first source node;
a second totem pole arrangement of a second NMOS transistor and a second PMOS transistor having source terminals electrically connected together at a second source node;
a first input terminal capacitively coupled to the first source node;
a second input terminal capacitively coupled to the second source node;
a first load having a net inductive reactance, electrically connected to drain terminals of the first and second NMOS transistors;
a second load having a net inductive reactance, electrically connected to drain terminals of the first and second PMOS transistors;
a first capacitor having a first terminal electrically connected to the first source node and a second terminal electrically connected to the first input terminal; and
a second capacitor having a first terminal electrically connected to the second source node and a second terminal electrically connected to the second input terminal; and
wherein each of the first NMOS transistor and the first PMOS transistor has a respective gate terminal electrically connected to the second terminal of the second capacitor and each of the second NMOS transistor and the second PMOS transistor has a respective gate terminal electrically connected to the second terminal of the first capacitor.
Claim 16
Claim 17
Claim 17
Claim 18
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (U.S. Patent 8,237,472 cited in the Information Disclosure Statement filed July 24, 2025, hereafter Kuo).
Claim 10: Kuo teaches a frequency multiplier (Figure 3B), comprising:
a capacitor circuit having a plurality of capacitors therein (CC1, CC2), said capacitor circuit responsive to a differential input signal (inputs at P3 and P4) applied to an inverting input node (P4) and a non-inverting input node (P3) thereof;
a frequency multiplication circuit (FMC) having a plurality of transistors therein (M5, M6), said FMC configured to receive components of the differential input signal passing through the plurality of capacitors (through CC1 and CC2 to the gates of M5 and M6), and multiply a frequency of the components of the differential input signal (column 5 lines 38-40); and
a plurality of inductor loads (LS1, LS2), which are connected to an inverting output node (and a non-inverting output node of the FMC (via D5 and D6) and are configured to convert a current signal generated by the FMC into a voltage signal (inherent in the functionality of an inductor).
Claim 11: Kuo further teaches that the FMC is configured to:
(i) receive the differential input signal through gates and sources of the plurality of transistors (the sources S5 and S6 are connected to P3 and P4, and the gates are connected to P3 and P4 via CC1 and CC2), and
(ii) output a differential signal (at D5 and D6), which has a multiplied frequency relative to the differential input signal, through the drains of the plurality of transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo.
Claim 12: Kuo teaches the limitations of claim 10 above. Kuo does not specifically teach that each of the plurality of capacitors has a capacitance that is at least ten (10) times a gate-source capacitance of each of the plurality of transistors. However, a capacitance that is at least ten (10) times a gate-source capacitance of each of the plurality of transistors would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a capacitance that is at least ten (10) times a gate-source capacitance of each of the plurality of transistors when employing the circuit of Kuo to maximize the overall performance of the circuit. Furthermore, such a provision of selecting a specific capacitance involves only routine design expedient.
Claim 13: Kuo teaches the limitations of claim 10 above. Kuo does not specifically teach the plurality of inductor loads has a resonant frequency that is twice a frequency of the differential input signal. However, a resonant frequency that is twice a frequency of the differential input signal would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a resonant frequency that is twice a frequency of the differential input signal when employing the circuit of Kuo to maximize the overall performance of the circuit. Furthermore, such a provision of selecting a specific resonant frequency involves only routine design expedient.
Allowable Subject Matter
Claims 1, 3, 7-9 and 14-20 would be allowed if the non-statutory double patenting rejections are resolved.
Regarding claims 1 and 14, the prior art does not fairly teach or suggest a first capacitor having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together, and a second terminal electrically coupled to the non-inverting input node; and a second capacitor having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together, and a second terminal electrically coupled to the inverting input node in combination with the limitations of claims 1 and 14.
KR102198548 (cited in the Information Disclosure Statement filed July 24, 2025, hereafter ‘548) shows first through fourth transistors (M1-M4; Figure 5a), a first capacitor (Cc) having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together (to VRF+), and a second capacitor (Cc) having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together. ‘548 does not specifically teach that the second terminal of the first capacitor is electrically coupled to the non-inverting input node (the other end of Cc is coupled to the gates of the transistors).
Claims 3, 7-9 and 15-20 are indicated as allowable merely for being dependent on claims 1 and 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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