DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on07/24/2025 is in compliance with the provisions on 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, lines 14-16, recites “the convolution processor to perform a convolution operation using the plurality of multiplying circuits on the signals that are output from the AD conversion circuit substrate directly to the plurality of multiplying circuits;”.
Examiner suggests amending the limitation to “the convolution processor to perform a convolution operation, using the plurality of multiplying circuits, on the signals that are output from the AD conversion circuit substrate directly to the plurality of multiplying circuits;”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 10,904,471 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the current limitations of claims 1-10 are broader than the Patent claims and are therefore encompassed therein by the Patent claims.
US Patent 10,904,471
Application No. 19/279427
Claim 1
A feature extracting element, comprising:
a light-receiving substrate where a plurality of light-receiving elements for photoelectrically converting received light are two-dimensionally arrayed; and
one or more other substrates that are laminated on the light-receiving substrate, wherein the one or more other substrates have:
an AD conversion circuit substrate to receive signals generated by the plurality of light-receiving elements and to convert the signals received from the plurality of light-receiving elements;
a convolution processor, connected to the light-receiving substrate via the AD conversion circuit substrate, having a plurality of multiplying circuits that are correspondingly provided per the light-receiving element or per a block that is configured of more than one light-receiving element among the plurality of the light-receiving elements, and performs a convolution operation using the plurality of multiplying circuits on the signals that are output from the AD conversion circuit substrate directly to the plurality of multiplying circuits; and
a pooling circuit to sample a signal that is output from the convolution processor, based on a predetermined condition.
Claim 1
A feature extracting element, comprising:
a light-receiving substrate including a plurality of light-receiving elements to photoelectrically convert received light, the plurality of light-receiving elements being two-dimensionally arrayed; and
one or more other substrates that are laminated on the light-receiving substrate, wherein the one or more other substrates include:
an AD conversion circuit substrate to receive signals generated by the plurality of light-receiving elements and to convert the signals received from the plurality of light-receiving elements;
a convolution processor, coupled to the light-receiving substrate via the AD conversion circuit substrate, having a plurality of multiplying circuits correspondingly provided per the light-receiving element or per a block configured of more than one light-receiving element among the plurality of the light-receiving elements, the convolution processor to perform a convolution operation using the plurality of multiplying circuits on the signals that are output from the AD conversion circuit substrate directly to the plurality of multiplying circuits; and
a pooling circuit to sample a signal output from the convolution processor, based on a predetermined condition.
Claim 1 of Patent 10,904,471 contains all the limitations of claim 1 of the application
Examiner notes:
Prior art teaches laminating AD circuit substrates and image signal processing substrates to a light-receiving substrate.
Strukov et al. (US 2012/0070038 A1): Strukov Figure 9 shows a light-receiving substrate laminated to an AD converter array and a digital signal processor multilayer circuit. Strukov further states “the DSP multilayer circuit (915) may be power/cost efficient and have extremely low latencies for in-situ low level signal processing tasks such as correlation or convolution of image data generated by a focal plane” in paragraph 0068.
Kolar et al. (US 2014/0354778 A1): Kolar teaches a laminated feature extraction element comprising a light-receiving substrate and one or more substrate laminated to the light-receiving substrate capable of performing convolution (Paragraph 0076).
Mabuchi (US 2008/0042046 A1): Mabuchi Figures 4-10 show various configurations of laminating a light-receiving substrate to an AD substrate and DSP substrate.
Kobayashi (US 2008/0284888 A1): Kobayashi Figures 14-16 show a light-receiving substrate laminated to various circuit substrates.
Prior art also teaches processors used to perform convolution processing.
Herrero Abellanas et al. (US 2015/0178246 A1): Herrero teaches a convolution processor including multiplying circuits and a pooling circuit.
However, the prior art, even in combination, is not seen to teach the signals that are output from the AD conversion circuit substrate directly to the plurality of multiplying circuits. That is, even if the teaching of the convolution processors of Herrero, Ling or Falcon was implemented in the signal processor of Strukov, Kolar, Mabuchi or Kobayashi, there is not teaching of the signals that are output from the AD conversion circuit substrate being directly input to the plurality of multiplying circuits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
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/WESLEY J CHIU/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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