The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (19/279,834) filed on July 24, 2025.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on July 24, 2025 have been considered and accepted.
Information Disclosure Statement
6.Acknowledgment is made of the information disclosure statements filed on July 24, 2025 and July 7, 2026. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Brewer et al. (US PGPUB 2020/0135720 hereinafter referred to as Brewer).
As per independent claim 1, Brewer discloses a device comprising: a first die [(Paragraphs 0020, 0036, 0046 and 0078; FIGs. 1-5, 8 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively to correspond to the claimed limitation], comprising: a first compute component, a second compute component, a first set of Through Silicon Vias (TSVs) associated with the first compute component and connecting stacked dies of the device [(Paragraphs 0020, 0036, 0046, 0078 and 0108-0117; FIGs. 1-5, 8 and related text) wherein Brewer teaches wherein FIG. 4 illustrates a top view of the processing logic die 106 having multiple processing logic partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i in accordance with some embodiments of the present disclosure. FIG. 4 shows each of the partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i having a separate FPGA 406. As shown, each of the nine FPGAs 406 illustrated in FIG. 4 has thirty-two input/output blocks 408 and sixteen logic blocks 410. Also, FIG. 4 shows programable or non-programable interconnects 412 between the input/output blocks 408 and the logic blocks 410 of each of the nine FPGAs 406. It is to be understood that the depiction of the amount of input/output units and logic units of an FPGA 406 is for convenience sake and that in some embodiments each FPGA of a partition could have more or less input/output units and logic units depending on the embodiment of the corresponding functional block; FIG. 9 illustrates a perspective view of the example 3D SIC 800 illustrated in FIG. 8 implementing ANN functional blocks (e.g., functional blocks 810, 812, and 814) and having non-volatile memory dies 102 and 104, a volatile memory die 108, and an ANN processing logic die 802 in accordance with some embodiments of the present disclosure. Specifically, FIG. 9 shows all the functional blocks of 3D SIC 800, i.e., FIG. 9 shows functional blocks 810, 812, 814, 910, 912, 914, 920, 922, and 924. It is to be understood that the 3D SIC 800, as shown in FIG. 9, has similar parts of the 3D SIC 100 of FIG. 5, except the processing logic die 802 is specifically configured to support or implement neurons. Thus, functional blocks of the 3D SIC 800 may or may not have the same physical structure as the functional blocks of the 3D SIC 100. With that said, it is to be understood that the memory dies (e.g., dies 102, 104, and 108), the TSVs (e.g., TSVs 116, 118, and 120), the interconnects (e.g., interconnects 122, 124, 126, and 128) are similar between the 3D SIC 100 and the 3D SIC 800 for the purposes of simplifying this disclosure. And, the functional blocks 810, 812, 814, 910, 912, 914, 920, 922, and 924 of the 3D SIC 800, as shown in FIG. 9, may or may not be similar in structure to the functional blocks 110, 112, 114, 210, 212, 214, 220, 222, and 224 of the 3D SIC 100, as shown in FIG. 5 to correspond to the claimed limitation], and a second set of TSVs associated with the second compute component and connecting the stacked dies of the device [(Paragraphs 0020, 0036, 0046, 0078 and 0108-0117; FIGs. 1-5, 8 and related text) wherein Brewer teaches wherein FIG. 4 illustrates a top view of the processing logic die 106 having multiple processing logic partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i in accordance with some embodiments of the present disclosure. FIG. 4 shows each of the partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i having a separate FPGA 406. As shown, each of the nine FPGAs 406 illustrated in FIG. 4 has thirty-two input/output blocks 408 and sixteen logic blocks 410. Also, FIG. 4 shows programable or non-programable interconnects 412 between the input/output blocks 408 and the logic blocks 410 of each of the nine FPGAs 406. It is to be understood that the depiction of the amount of input/output units and logic units of an FPGA 406 is for convenience sake and that in some embodiments each FPGA of a partition could have more or less input/output units and logic units depending on the embodiment of the corresponding functional block, as shown in FIG. 9, has similar parts of the 3D SIC 100 of FIG. 5, except the processing logic die 802 is specifically configured to support or implement neurons. Thus, functional blocks of the 3D SIC 800 may or may not have the same physical structure as the functional blocks of the 3D SIC 100. With that said, it is to be understood that the memory dies (e.g., dies 102, 104, and 108), the TSVs (e.g., TSVs 116, 118, and 120), the interconnects (e.g., interconnects 122, 124, 126, and 128) are similar between the 3D SIC 100 and the 3D SIC 800 for the purposes of simplifying this disclosure. And, the functional blocks 810, 812, 814, 910, 912, 914, 920, 922, and 924 of the 3D SIC 800, as shown in FIG. 9, may or may not be similar in structure to the functional blocks 110, 112, 114, 210, 212, 214, 220, 222, and 224 of the 3D SIC 100, as shown in FIG. 5 to correspond to the claimed limitation]; and a second die, stacked on the first die [(Paragraphs 0020, 0036, 0046; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation], comprising: a first memory bank module connected to the first compute component using the first set of TSVs, and a second memory bank module connected to the second compute component using the second set of TSVs [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 2 illustrates a top view of the non-volatile memory die 102 having multiple non-volatile memory partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i in accordance with some embodiments of the present disclosure. The partitions can be arranged in a second direction (i.e., perpendicular to the first direction of the stacking of the dies of the 3D IC). Each of the partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i has multiple non-volatile memory elements. Each of the partitions illustrated in FIG. 2 shows nine non-volatile memory element clusters 206. And, each of the non-volatile memory element clusters 206 shows nine non-volatile memory elements 208. Thus, each of the partitions illustrated in FIG. 2 has eighty-one memory elements 208. However, it is to be understood that the depiction of eighty-one memory elements is for convenience sake and that in some embodiments each partition could have up to at least a billion memory elements. To put it another way, the number of memory elements per non-volatile memory partition can be enormous and vary greatly. Also, it is to be understood that non-volatile memory die 102 and non-volatile memory die 104 are similar or exactly the same with respect to structure and design to correspond to the claimed limitation].
As per dependent claim 2, Brewer discloses a third die, stacked on the second die, comprising: a third memory bank module connected to the first compute component using the first set of TSVs; and a fourth memory bank module connected to the second compute component using the second set of TSVs [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 2 illustrates a top view of the non-volatile memory die 102 having multiple non-volatile memory partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i in accordance with some embodiments of the present disclosure. The partitions can be arranged in a second direction (i.e., perpendicular to the first direction of the stacking of the dies of the 3D IC). Each of the partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i has multiple non-volatile memory elements. Each of the partitions illustrated in FIG. 2 shows nine non-volatile memory element clusters 206. And, each of the non-volatile memory element clusters 206 shows nine non-volatile memory elements 208. Thus, each of the partitions illustrated in FIG. 2 has eighty-one memory elements 208. However, it is to be understood that the depiction of eighty-one memory elements is for convenience sake and that in some embodiments each partition could have up to at least a billion memory elements. To put it another way, the number of memory elements per non-volatile memory partition can be enormous and vary greatly. Also, it is to be understood that non-volatile memory die 102 and non-volatile memory die 104 are similar or exactly the same with respect to structure and design to correspond to the claimed limitation].
As per dependent claim 3, Brewer discloses wherein the first memory bank module connected to the first compute component using the first set of TSVs forms a first processing element configured to perform a compute function utilizing data from the first memory bank module, and the second memory bank module connected to the second compute component using the second set of TSVs forms a second processing element configured to perform a compute function utilizing data from the second memory bank module [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation].
As per dependent claim 4, Brewer discloses a plurality of interconnected ports of the first die connecting the first processing element and the second processing element to one or more additional processing elements, wherein the first compute component and the second compute component comprise compute circuitry configured to perform the compute function and the one or more additional processing elements comprise a compute component connected to at least one memory bank module from an array of memory bank modules arranged on the first die stacked thereon and using corresponding sets of TSVs [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation].
As per dependent claim 5, Brewer discloses wherein for the one or more additional processing elements, their respective compute components are configured to perform a compute function on data from their respective at least one memory bank module that is stacked thereon [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation].
As per dependent claim 6, Brewer discloses a controller programmed to execute a transfer of the data between the first compute component and the first memory bank module, a transfer of the data between the second compute component and the second memory bank module, and for the one or more additional processing elements, a transfer of the data between their respective compute component and their respective at least one memory bank module [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation].
As per dependent claim 7, Brewer discloses wherein the first set of TSVs and the second set of TSVs are among a plurality of TSVs distributed in a plurality of areas of the first die [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation].
As per dependent claim 8, Brewer discloses wherein the first set of TSVs comprises at least one of the plurality of TSVs in a first area of the first die contacting the first compute component, the second set of TSVs comprises at least one of the plurality of TSVs in a second area of the first die contacting the second compute component [(Paragraphs 0020, 0036, 0040-0048; FIGs. 1, -5 and related text) wherein Brewer teaches wherein FIG. 1 illustrates a front view of a 3D SIC 100 having multiple non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 in accordance with some embodiments of the present disclosure. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (as shown in FIG. 1) as well as functional blocks 210, 212, 214, 220, 222, and 224 (as shown in FIGS. 2-5) that traverse and are perpendicular to the multiple non-volatile memory dies 102 and 104, the volatile memory die 108, and the processing logic die 106. The 3D SIC 100 also has TSVs 116, TSVs 118, and TSVs 120 that connect the dies respectively. TSVs 116 are shown in between and connecting the non-volatile memory die 102 to the non-volatile memory die 104. TSVs 118 are shown in between and connecting the non-volatile memory die 104 to the processing logic die 106. TSVs 120 are shown in between and connecting the processing logic die 106 to the volatile memory die 108. It is to be understood that all the TSVs described herein pass through the dies described herein even thought this may not be clear from the drawings. For example, TSVs 116, TSVs 118, and TSVs 120 are parts of single TSVs passing through the dies of the 3D SIC 100 to correspond to the claimed limitation].
As per dependent claim 9, Brewer discloses wherein the first processing element additionally comprises the third memory bank module and is configured to perform a compute function utilizing data from the third memory bank module, and the second processing element additionally comprises the fourth memory bank module and is configured to perform a compute function utilizing data from the fourth memory bank module [(Paragraphs 0092-095; Figs. 1-5) where 3D SICs having functional blocks configured to accelerate or implement ANN computation. Also, in general, aspects of the present disclosure are directed to 3D ICs having functional blocks configured to accelerate or implement ANN computation. As illustrated herein, delineated blocks or columns of stacked chips, in a second direction that is orthogonal to the first direction (e.g., a horizontal direction), are configured to support or implement an ANN. Each block or column can be considered a separate ANN region configured to support the ANN. To put it another way, each block or column is adapted to locally host a portion of the data of a large model (e.g., ANN) and at least handle or accelerate the data intensive operations on the local data using the local processing capacity in the block or column. The stack or array of blocks/columns have communication facility to allow data exchange among the blocks to process the interactions among the portions of the large model. A device of multiple stacked chips has a distribution, in a second direction that is orthogonal to the first direction (e.g., a horizontal direction), of the ANN regions that are connected via a grid network internal to the device. The connections of the grid network allow for fast access to neuron set output between neighboring ANN regions. The network can be scaled up by stacking in a first direction (e.g., vertically) for 3D integration and use a larger chip area for 2D integration. Also, multiple devices (e.g., multiple 3D SICs) can be further connected via a bus or computer network to implement or support a large ANN. In some embodiments, a functional block of the device, which supports the ANN, can be a functional block similar to the functional blocks illustrated in FIGS. 1-5, in that the functional block is a general data processing block instead of a block specifically hardwired for supporting an ANN. In some other embodiments, the functional block of the device, which supports the ANN, can include specific hardware circuitry for artificial intelligence (Al) acceleration, such as specific hardware circuitry that includes units for or used in vector and/or matrix algebra calculations. Whether the functional block is more general or specifically adapted for an ANN, the hardware circuitry of the block can include adders and/or multipliers in the processing logic layer of the block (e.g., the respective processing logic partition of a processing logic die stacked in the device can include adders and/or multipliers). That way, processing units can be programmed for different types of neural network computations or a combination of neural network computations and other types of computations to correspond to the claimed limitation].
As per dependent claim 10, Brewer discloses wherein the stacked dies of the device comprise a plurality of additional dies stacked on the third die [(Paragraphs 0044 and 0056; Figs. 1-5) where FIG. 3 illustrates a top view of the volatile memory die 108 having multiple volatile memory partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i in accordance with some embodiments of the present disclosure. The partitions can be arranged in second direction (i.e., perpendicular to the direction of the stacking of the dies of the 3D IC). Each of the partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i has multiple volatile memory elements. Each of the partitions illustrated in FIG. 3 shows nine volatile memory element clusters 306. And, each of the volatile memory element clusters 306 shows nine volatile memory elements 308. Thus, each of the partitions illustrated in FIG. 3 has eighty-one memory elements 308. However, it is to be understood that the depiction of eighty-one memory elements is for convenience sake and that in some embodiments each partition could have up to at least a billion memory elements. To put it another way, the number of memory elements per volatile memory partition can be enormous and vary greatly to correspond to the claimed limitation].
As per dependent claim 11, Brewer discloses Dynamic Random Access Memory (DRAM) dies, wherein one or more of the second die or the third die comprises a DRAM die [(Paragraphs 0034, 0043-0044 and 0105; Figs. 1 and 3-5) where the 3D SIC can have a volatile memory die (such as a DRAM die or a static random access memory (SRAM) die) including an array of volatile memory partitions. Each partition of the array of volatile memory partitions can include an array of volatile memory cells and each cell can have a corresponding address. FIG. 3 illustrates a top view of the volatile memory die 108 having multiple volatile memory partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i in accordance with some embodiments of the present disclosure. The partitions can be arranged in second direction (i.e., perpendicular to the direction of the stacking of the dies of the 3D IC).
Each of the partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i has multiple volatile memory elements. Each of the partitions illustrated in FIG. 3 shows nine volatile memory element clusters 306. And, each of the volatile memory element clusters 306 shows nine volatile memory elements 308. Thus, each of the partitions illustrated in FIG. 3 has eighty-one memory elements 308. However, it is to be understood that the depiction of eighty-one memory elements is for convenience sake and that in some embodiments each partition could have up to at least a billion memory elements. To put it another way, the number of memory elements per volatile memory partition can be enormous and vary greatly to correspond to the claimed limitation].
As per dependent claim 12, Brewer discloses wherein the compute function comprises one or more of: matrix multiplication; dot products; activation function; or a mathematical function associated with an Artificial Intelligence (Al) application [(Paragraphs 0110-0115; Figs. 8 and 9) where the functional block of the array of functional blocks of 3D SIC 800 (e.g., functional block 810, 812, 814, 910, 912, 914, 920, 922, or 924) can include a respective processing logic partition including a hardware circuit configured to perform the computation of an activation function. The activation function can include a sigmoid activation function or a radial basis function. Also, other types of activation functions can be performed by the hardware circuit. The activation function can be a step function, a linear function, or a log-sigmoid function. With a complex function (e.g., log-sigmoid function, sigmoid function, etc.), it may be preferable to implement the processing logic partition with a specifically configured circuit for improved efficiency, such as by using an ASIC. Otherwise, it may be advantageous to use a FPGA to correspond to the claimed limitation].
As for independent claims 13 and 20, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 14, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claim 15, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
As for dependent claim 16, the applicant is directed to the rejections to claim 11 set forth above, as they are rejected based on the same rationale.
As for dependent claim 17, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
As for dependent claim 18, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
As for dependent claim 19, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kellam et al., US PGPUB 2022/0269436 – teaches COMPUTE ACCELERATED STACKED MEMORY.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571)270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
Prosecution Insights