DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-5, 7, 8, 13, 15, and 17-20 are rejected under 35 U.S.C. 102(1)(1) as being anticipated by Gendler et al. (US 2016/0378660), “Gendler”.
2. As per claim 1, Gendler discloses processor circuitry configured to operate on data in multiple memory address spaces [processor core 102 operating on data in storage devices, figure 1]; and data cache circuitry configured to store data for the processor circuitry, the data including data from the multiple memory address spaces at a first cache level [cache 106, figure 1] including a first data subset from a first memory address space [a cache line, paragraph 32], wherein the data cache circuitry includes: tag circuitry configured to identify, in a single clock cycle, all entries in the data cache circuitry that currently store data of the first data subset from the first memory address space [flushing the cache line in a single clock cycle, paragraph 32].
3. As per claim 2, Gendler discloses invalidate control circuitry configured to invalidate, in the single clock cycle, all the identified entries in the data cache circuitry [flush/invalidate, paragraph 46].
4. As per claim 3, Gendler discloses flush control circuitry configured to flush the identified entries in the data cache circuitry [flush/invalidate, paragraph 46] to another cache level in a cache hierarchy [multiple levels of cache, paragraph 13].
5. As per claim 4, Gendler discloses control circuitry configured to track occupancy of data in the data cache circuitry from a first memory address space; and occupancy of data in the data cache circuitry from a second memory address space [multiple levels of cache, paragraph 13] [cache fullness/occupancy inherently monitored].
6. As per claim 5, Gendler discloses wherein the control circuitry is further configured to determine a retention priority for a cache line of the data cache circuitry that stores data for the first memory address space based on the tracked occupancy for the first memory address space [eviction policy inherent in cache devices].
7. As per claim 7, Gendler discloses wherein the control circuitry is configured to maintain a minimum occupancy level for a first type of memory address space [zero level].
8. As per claim 8, Gendler discloses wherein the control circuitry is configured to prevent a type of memory address space from exceeding a threshold occupancy level [memory full].
9. As per claim 13, Gendler discloses wherein the data cache circuitry is configured to store and provide data at different cache line sizes for different memory address spaces of the multiple memory address spaces [multiple levels of cache, paragraph 13].
10. As per claim 15, Gendler discloses write buffer circuitry configured to buffer data to be written to data bank circuits of the data cache circuitry; read buffer circuitry configured to buffer data read from the data bank circuits; and transpose circuitry configured to transpose data for the write buffer circuitry and from the read buffer circuitry [read and ordering buffer implanted on the same system, paragraph 46].
11. As per claims 17-20, the examiner directs the applicant’s attention to claims rejection above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Gendler et al. (US 2016/0378660), “Gendler”, in view of Steely et al. (US 2014/0006717), “Steely”.
2. As per claim 16, Gendler discloses the processor circuitry [figure 1].
Gendler does not disclose expressly a graphics processor.
Steely discloses a GPU in paragraph 114.
Gendler and Steely are analogous art because they are from the same field of endeavor of storage device management.
Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Gendler by including the GPU as taught by Steely in paragraph 114.
The motivation for doing so would have been performance improvement as expressly taught by Steely in paragraph 114.
Conclusion
A. Allowable Subject Matter
Claims 6, 9-12, and 14 are objected to. The closest prior art of record, “Gendler” discloses cache flushing in paragraph 32.
The primary reasons for allowance of claim 6 in the instant application is the combination with the inclusion in these claims that “wherein the determination includes to: assign a first retention priority to the cache line for a first tracked occupancy level; and assign a second retention priority to the cache line for a second tracked occupancy level, wherein the second retention priority is higher than the first retention priority and the second tracked occupancy level is lower than the first tracked occupancy level”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 9 in the instant application is the combination with the inclusion in these claims that “wherein the tag circuitry is configured to identify all the entries in the data cache circuitry that currently store data for the first memory space using parallel tag check operations across multiple tag bank circuits”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 11 in the instant application is the combination with the inclusion in these claims that “wherein the data cache circuitry is configured to store tag information for an entry that includes: a tag portion of an address of cached data in the entry; and memory address space information that identifies one of the multiple memory address spaces from which data is stored at the first cache level, wherein the tag circuitry is configured to identify all the entries in the data cache circuitry that currently store data for the first memory address space based on the memory address space information”. The prior art of record neither anticipates nor renders obvious the above recited combination.
The primary reasons for allowance of claim 14 in the instant application is the combination with the inclusion in these claims that “wherein the tag circuitry is configured to perform, at least partially in parallel in a given clock cycle: a first tag check for a request to first memory address space; and a second tag check for a request to a second memory address space”. The prior art of record neither anticipates nor renders obvious the above recited combination.
As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP.
B. Claims Rejected
Claims 1-5, 7, 8, 13, and 15-20 are rejected.
C. Direction for Future Remarks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAE U YU/Primary Examiner, Art Unit 2138
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