DETAILED ACTION
Claims 1-20 are pending.
Priority: 7/31/2024(Pro)
Assignee: Micron
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2, 3, 4, 7-8, 10, 11, 12, 15-16 18, 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
I. Antecedent Basis
1.Claims 2, 10, 18 are rejected for reciting a limitation with antecedent basis issues.
Claim 2 recites, ‘selecting, from the plurality of second block stripes, a second block stripe….’. However claim 1 already introduces ‘a second block stripe’ as it recites, ‘selecting, from the plurality of second block stripes, a second block stripe’. Claims 10, 18 have the same issue.
2.Claims 3, 11 are rejected for narrowing or altering the antecedent basis in an ambiguous way instead of adding a true further limitation.
Claim 3 recites, ‘selecting a first second block stripe of the plurality of second block stripes as the destination block stripe’.
However claim 1 recites, ‘selecting from the plurality of second block stripes a second block stripe as a destination block stripe’.
Claim 1 selects a broad ‘second block stripe’. Dependent claim 3 introduces ‘a first second block stripe’, which creates a confusing naming contradiction rather than cleanly specifying a further limitation.
Using ‘first second’ creates ambiguity about whether a new structural element is introduced or if it improperly redefines a term already set in the parent claim 1. Hence claim 3 is rejected. Claim 11 has the same issue.
II. Lack of Clarity
1.Claims 4, 7-8, 12, 15-16, 19-20 are rejected for reciting limitations that are unclear, vague and indefinite.
Claim 8 recites, ‘the occupancy threshold corresponds to a number of codewords to be programmed to the destination block stripe’.
The spec fails to define what constitutes ‘codewords’ in the claimed context of NVM garbage collection or folding. Therefore the term ‘codewords’ is a vague, unguided mathematical metric.
The phrase ‘number of codewords’ is a term of degree or a relative parameter without any established baseline, standard, or conversion factor provided in the disclosure. There is no algorithm, lookup table, or explicit disclosure explaining how the ‘number of codewords’ is determined or derived, in the claimed context of NVM GC or folding.
Hence claim 8 is indefinite because its language, read in light of the spec, fails to inform the scope of the disclosure with reasonable certainty. Claim 16 has the same issue.
Claim 7 is also indefinite as it recites, ‘wherein the occupancy criterion is satisfied if a valid codeword count is equal to or exceeds an occupancy threshold’. The spec fails to define what constitutes ‘a valid codeword’, ‘a valid codeword count’ and how they are determined in the claimed context. Claims 15, 20 have the same issue.
Claims 4, 12, 19 have the same issue as they recite, ‘maintaining a valid codeword count’. Claim 4 further recites, ‘….incrementing the valid codeword count by a number of valid codewords in the respective first block stripe’, but it is unclear how ‘a number of valid codewords’ is determined. If the valid codeword count is maintained/constant, then how is it incremented? Claims 12, 19 have the same issue.
Because the terms are not defined in the spec, they lack an objective standard. In addition, the inventor’s failure to act as their own lexicographer leaves the scope of the claims unclear. Hence claims 4, 7-8, 12, 15-16, 19-20 are rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-11, 13-18, 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wei (20230017946) in view of Sharon et al (20210349778) and Ohno (20130246842).
As per Claim 1, Wei discloses a system (Wei, [0021 - Fig. 1 shows computing system 100 that includes memory subsystem 110]) comprising:
- a memory sub-system (Wei, [0022 – In Fig. 1, memory subsystem 110 can be a storage device such as SSD, a flash drive, USB flash drive, HDD, DIMM, NVDIMM etc.]) comprising:
- a cache comprising a plurality of a first number of bits per cell memory cells (Wei, [0014 - A SLC can store one bit of information and has two logic states]) associated with a plurality of first block stripes (Wei, [0028 – In Fig. 1, memory device 130 can be a NVM device that include NAND flash memory and write-in-place memory, such as a 3D cross-point memory device, which is a cross-point array of NVM cells]; [0013 - For NAND memory devices, each plane consists of a set of physical blocks, which are groups of memory cells to store data]);
- a storage comprising a plurality of a second number of bits per cell memory cells (Wei, [0014 - multi-level cells/MLCs]) associated with a plurality of second block stripes (Wei, [0014 - Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. There are various types of cells, MLCs, TLCs, and QLCs]; [0038 - Memory subsystem 110 can perform writing/programming operations on free block stripes, e.g., erased block stripes]),
- wherein the second number of bits per cell (Wei, [0014 - multi-level cells/MLCs]) is greater than the first number of bits per cell (Wei, [0014 - single-level cells/SLCs]);
- a processing device (Wei, [Fig. 1: processor 117]), operatively coupled with the cache and the storage (Wei, [0035 - memory devices 130 include local media controllers 135 that operate with memory subsystem controller 115 to execute operations on memory cells of memory devices 130]), to perform operations (Wei, [0035 – In Fig. 1, memory subsystem controller 115 manages the memory device 130, e.g., perform media management operations on memory device 130]) comprising:
- responsive to initiating a media management operation (Wei, [0058 – In Fig. 5, at step 502, the processing device determines whether garbage collection/GC is to be performed on memory device 130 to free up one or more block stripes in memory subsystem 110. Whether GC is to be performed is based on the number of free block stripes/second block stripes]; [Fig. 2: step 202]), selecting, from the plurality of second block stripes (Wei, [0038 - The number of free block stripes in memory subsystem 110 is less than GC threshold]), a second block stripe as a destination block stripe for the media management operation (Wei, [0059 – In Fig. 5, at step 504, processing device selects a candidate block stripe for folding into a target/destination block stripe in response to determining that GC is to be performed]);
- selecting, from the plurality of the first block stripes (Wei, [0019 - Valid and invalid translation units within each candidate block stripe identifies first block stripes]; [0049 - Fig. 3A shows L2P table 300, which includes a set of L2P entries 3021-302X. Each of the L2P entries corresponds to a logical address, a physical address, including a block number, a page number, a translation unit number, and a plane number]), one or more first block stripes satisfying an occupancy criterion (Wei, [Fig. 5: step 560]; [0016 – GC uses a valid page/VP bitmap that logs/tracks valid translation units for each block stripe]; [0039 - Memory subsystem 110 utilizes a P2L table for determining valid translation units/valid data in the candidate block stripe such that folding can be performed. If P2L is unavailable, L2P table is utilized because it is shared across all block stripes of the memory devices 130]) as a set of source block stripes for the media management operation (Wei, [Fig. 2 presents a flow diagram as a loop which selects one or more first block stripes as a set of source block stripes for GC]; [0038 - GC policy causes the processing device to select a candidate/first block stripe based on a valid translation unit count/VTC, which indicates how many valid translation units/valid data are present in the block stripe. The processing device selects a block stripe as the candidate block stripe that has a highest VTC or a VTC that satisfies a threshold; Neither the claim nor the spec disclose how ‘valid codeword count’ and ‘number of codewords’ are derived. Since a single block of ‘valid data’ consists of several encoded codewords, it is valid to imply that the occupancy criterion is satisfied if the valid codeword count is equal to or exceeds the occupancy threshold/highest VTC]);
- performing the media management operation (Wei, [0062 – In Fig. 5, step 510, the processing device performs folding of the candidate block stripe into the target block stripe using an L2P table]),
- wherein the media management operation relocates valid data (Wei, [0040 - During GC, the processing device identifies all valid translation units in a candidate block stripe and folds/copies these valid translation units/valid data into the target block stripe, thereby relocating valid data]) from the set of source block stripes to the destination block stripe (Wei, [0062 – In Fig. 5, step 510, if the block, page, and translation unit numbers of an entry in the L2P table matches with the block, page, and translation unit numbers of a translation unit of the candidate block stripe, this identifies a valid translation unit within the block stripe, which should be folded/copied before the block stripe can be erased. This process is continued until each translation unit is identified as either being valid or invalid, such that valid translation units can be folded into the target block stripe]).
In Para-0016, Wei discloses that a die can include 500 block stripes. Accordingly Sharon discloses block stripes, codewords, SLCs, MLCs and folding as follows,
a memory sub-system (Sharon, [Fig. 1: memory system 100]; [0048 – In Figs. 1-5, each memory die in integrated memory assembly 104 utilizes NAND flash memory]; [0047 – In Figs. 1-5, memory system 100 comprises memory controller 102, integrated memory assembly 104 for storing data and local memory 106]; [0064 – In Figs. 4-5, on-die ECC engine 330 encodes data bits from memory controller 102 into codewords that contain the data bits and parity bits]; [0048 – In Figs. 1-5, each integrated memory assembly 104 includes one or more memory die and one or more control die; This implies that a grouping of blocks with the same index across those dies is a block stripe or superblock]) comprising:
a cache (Sharon, [Figs. 27A-27D: SLC cache 1902,1904,1906]) comprising a plurality of a first number of bits per cell memory cells (Sharon, [0164 - Fig. 17A is a graph of threshold voltage versus number of memory cells, when each memory cell stores single bit per memory cell data. Memory cells that store single bit per memory cell data are SLC]) associated with a plurality of first block stripes (Sharon, [0119 – In Fig. 9 integrated memory assembly 104 shows two memory die 302a, 302b and each die has a plurality of blocks; So Block 0 from Die 1 combined with Block 0 from Die 2 form a sequence]);
a storage (Sharon, [Figs. 27A-27D: MLC storage 1908]) comprising a plurality of a second number of bits per cell memory cells (Sharon, [0165 - Fig. 17B shows threshold voltage distributions for the memory array when each memory cell stores multiple bit per memory cell data. Memory cells that store multiple bit per memory cell data are MLC]) associated with a plurality of second block stripes,
wherein the second number of bits per cell (Sharon, [Fig. 17B: MLC, 4 voltage states, stores 2 bits]) is greater than the first number of bits per cell (Sharon, [Fig. 17A: SLC, 2 voltage states, stores 1 bit]; [0046 - The control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the integrated memory assembly of Sharon into the optimized GC process of Wei, for the benefit of the control die performing an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data (Sharon, Abstract).
Wei, Sharon disclose that data and parity comprise a codeword. Ohno clarifies satisfying the occupancy criterion as follows,
selecting, from the plurality of the first block stripes, one or more first block stripes (Ohno, [0035 – In Fig. 1, blocks of stripes S1 through Sn are configured to store data items and error-correcting codes/parity for the data items, i.e. codewords]) satisfying an occupancy criterion (Ohno, [0105 - Fig. 10 shows data number management table T1, where information of ‘stripe S(i)’ and ‘the number of data items on a per-stripe basis’ is stored; Each data item and its parity form a codeword. So ‘number of data items’ for each stripe is equivalent to the number of codewords]; [0110 – In Fig. 11, ‘stripe S(i)’ is stripe identification and ‘presence of data on a per-stripe basis’ indicates whether data/valid data is present on a per-stripe basis]) as a set of source block stripes (Ohno, [0036 – In Fig. 1, selecting unit 12 selects, as a source stripe, a stripe in which at least one of the blocks stores a data item and another one of the blocks stores an error-correcting code for the data item, among stripes S1 through Sn each including a group/set of storage areas of a plurality of blocks that are located one on each of the storage devices 11-1 through 11-N]) for the media management operation (Ohno, [0038 - The moving unit 14 moves the data item stored in the source stripe to the available block of the destination stripe]);
Wei, Sharon disclose that storing data as multiple bit per memory cell data increases the capacity of the storage device.
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage expansion of Ohno into the optimized GC process of Wei, Sharon for the benefit of using a technique that moves data stored in the source stripe to the destination stripe, and reconfigures the stripes to expand the storage area capacity. This technique describes a form of garbage collection combined with a wear-leveling or capacity-expansion mechanism often called folding, compaction, or block migration typically managed by the FTL in NVM devices (Ohno, 0007).
As per Claim 2, the rejection of claim 1 is incorporated, and Wei discloses,
- wherein selecting the destination block stripe comprises:
- selecting, from the plurality of second block stripes, a second block stripe (Wei, [0054 – In Fig. 2, step 222, the processing device selects a new candidate block stripe and performs GC/garbage collection on this new/second candidate block stripe; Here ‘a second block stripe’ is interpreted as any stripe from the plurality of second block stripes]) having a lowest number of program erase cycles (PECs) as the destination block stripe (Wei, [0054 - The aggressive GC policy allows the pausing and/or aborting of processing the L2P candidate block stripe, which requires an L2P table-based search, and optionally considers several factors in selecting a new candidate block stripe, including a number of PECs for a block stripe etc.]; [0047 - A high number of PEC for a block stripe can indicate that the block stripe is old, which can indicate that it is susceptible to more errors than a block stripe with a lower number of PEC, thereby implying that since GC was performed on new/second candidate block stripe, it had the lowest PECs]).
As per Claim 3, the rejection of claim 1 is incorporated, and Wei discloses,
- wherein selecting the destination block stripe (Wei, [Figs. 2, 5]) comprises:
- selecting a first second block stripe of the plurality of second block stripes as the destination block stripe (Wei, [0059 - In Fig. 5, after step 502, at step 504, the processing device selects a candidate block stripe for folding into a target/destination/free block stripe in response to determining that GC is to be performed]).
Ohno clarifies,
selecting a first second block stripe of the plurality of second block stripes as the destination block stripe (Ohno, [0037 – In Fig. 1, selecting unit 13 selects, as a destination stripe, a stripe in which at least one of the blocks stores a data item and in which the number of available blocks is equal to or greater than the number of blocks of the source stripe which store data items, among the stripes other than the source stripe]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage expansion of Ohno into the optimized GC process of Wei, Sharon for the benefit of using a GC technique that moves data stored in the source stripe to the destination stripe, and reconfigures the stripes to expand the storage area capacity (Ohno, 0007).
As per Claim 5, the rejection of claim 1 is incorporated, and Wei, Sharon, Ohno disclose,
- wherein the plurality of first block stripes is chronologically ordered from a first block stripe programmed first to a first block stripe programmed last (Ohno, [0106 – In Fig. 10, the information in stripe S(i) is identification information/stripe number of a stripe. The stripe numbers are sequentially/chronological assigned to stripes in block address order]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage expansion of Ohno into the optimized GC process of Wei, Sharon for the benefit of using a GC technique that moves data stored in the source stripe to the destination stripe, and reconfigures the stripes to expand the storage area capacity (Ohno, 0007).
As per Claim 6, the rejection of claim 1 is incorporated, and Wei, Sharon, Ohno disclose,
- wherein the plurality of first block stripes is ordered from a first block stripe having a lowest number of valid codewords to a first block stripe having a largest number of valid codewords (Ohno, [Fig. 10]; [0146 – In Fig. 17, the data allocation control unit 21 searches for a stripe in which the number of data items C is small, implying small number of codewords. The source stripe is searched for by searching the stripes from the one with the highest stripe number to the one with the lowest stripe number. More specifically, the stripe S(n−1), the stripe S(n−2),…, the stripe S(2), the stripe S(1), and the stripe S(0) are searched in this order, thereby implying that the stripes are stored in ascending order of codewords]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage expansion of Ohno into the optimized GC process of Wei, Sharon for the benefit of using a GC technique that moves data stored in the source stripe to the destination stripe, and reconfigures the stripes to expand the storage area capacity (Ohno, 0007).
As per Claim 7, the rejection of claim 1 is incorporated, and Wei, Sharon, Ohno disclose,
- wherein the occupancy criterion is satisfied if a valid codeword count (Ohno, [Figs. 10-12]; [0112 - In Fig. 11, D2(3)=1 indicates that the stripe of the number 3 on the hard disk of the number 2 stores effective data/valid codeword]; [0035 - The blocks of the stripes S1 through Sn are configured to store data items and error-correcting codes/parity for the data items, thereby implying that data items and corresponding parity are the codewords]) is equal to or exceeds an occupancy threshold (Ohno, [0037 - The selecting unit 13 selects, as a destination stripe, a stripe in which at least one of the blocks stores a data item and in which the number of available blocks is equal to or greater than the number of blocks of the source stripe which store data items, among the stripes other than the source stripe]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage expansion of Ohno into the optimized GC process of Wei, Sharon for the benefit of using a GC technique that moves data stored in the source stripe to the destination stripe, and reconfigures the stripes to expand the storage area capacity (Ohno, 0007).
As per Claim 8, the rejection of claim 7 is incorporated, and Wei, Sharon, Ohno disclose that a die can include 500 block stripes.
Accordingly Sharon discloses,
- wherein the occupancy threshold corresponds to a number of codewords (Sharon, [0039 - Codewords are stored in the memory die. Each codeword may contain data bits and parity bits]; [0077 - Fig. 5 shows four sets of data latches 360(1), 360(2), 360(3), 360(4). Each set stores a codeword for a different page]) to be programmed to the destination block stripe (Sharon, [Fig. 9 shows a block stripe as a collection of blocks, one from each die]; [0078 – In Figs. 4-5, control circuitry 310 stores the codewords into non-volatile memory cells in the memory structure 326]; [0077 – In Fig. 5, while a codeword is stored in latches 360 or in storage region 318, control die 304, e.g., data folding circuit 334, may perform a folding process on the data]; [0077 – In Fig. 5, four bits are stored per memory cell, four pages are stored in a set of memory cells]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the integrated memory assembly of Sharon into the optimized GC process of Wei, for the benefit of the control die performing an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data (Sharon, Abstract).
Neither the claim nor the spec define ‘codeword’ or ‘codewords’ or determining ‘a number of codewords’.
Ohno discloses,
- wherein the occupancy threshold corresponds to a number of codewords to be programmed to the destination block stripe (Ohno, [0035 - The blocks of the stripes S1 through Sn are configured to store data items and error-correcting codes/parity for the data items, thereby implying that data items and corresponding parity are the codewords]; [0107 – In Fig. 11, the information in ‘the number of data items on a per-stripe stripe basis’ indicates the number of data items stored in a stripe; Since each data item has its parity, it therefore implies that the number of data items on each stripe provides the number of codewords to be programmed to the destination stripe]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the storage expansion of Ohno into the optimized GC process of Wei, Sharon for the benefit of using a GC technique that moves data stored in the source stripe to the destination stripe, and reconfigures the stripes to expand the storage area capacity (Ohno, 0007).
As per Claim 9, it is similar to claim 1 and therefore the same mappings are incorporated.
As per Claim 10, it is similar to claim 2 and therefore the same mappings are incorporated.
As per Claim 11, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 13, it is similar to claim 5 and therefore the same mappings are incorporated.
As per Claim 14, it is similar to claim 6 and therefore the same mappings are incorporated.
As per Claim 15, it is similar to claim 7 and therefore the same mappings are incorporated.
As per Claim 16, it is similar to claim 7 and therefore the same mappings are incorporated.
As per Claim 17, it is similar to claims 1,9 and therefore the same mappings are incorporated.
As per Claim 18, it is similar to claim 2 and therefore the same mappings are incorporated.
As per Claim 20, it is similar to claim 7 and therefore the same mappings are incorporated.
Claims 4, 12, 19 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Wei (20230017946) in view of Sharon et al (20210349778), Ohno (20130246842) and Manning et al (20200272538).
As per Claim 4, the rejection of claim 1 is incorporated, and Wei
discloses,
- wherein selecting the set of source block stripes (Wei, [Figs. 1-2, 5]) comprises:
- maintaining a valid codeword count (Wei, [0038 - A GC policy can cause the processing device to select a candidate block stripe based on a valid translation unit count/VTC, which indicates how many valid translation units are present in the block stripe; Here VTC is equivalent to ‘a valid codeword count’. Since the claim does not define the term, the recitation is a valid interpretation]);
- for each first block stripe of the plurality of first block stripes, determining whether the valid codeword count satisfies the occupancy criterion (Wei, [0016 - A GC procedure can use a valid page/VP bitmap that logs/tracks valid translation units for each block stripe]; [0038 - The processing device selects a block stripe as the candidate block stripe that has a highest VTC or a VTC that satisfies a threshold; Since a single block of ‘valid data’ consists of several encoded codewords, it is valid to imply that the occupancy criterion is satisfied if the valid codeword count is equal to or exceeds the occupancy threshold/highest VTC]);
- responsive to determining that the valid codeword count does not satisfy the occupancy criterion (Wei, [0042 – In Fig. 2, in response to determining that the number of free block stripes does not satisfy the minimum threshold, .i.e., the number of free block stripes is less than the minimum threshold, implying that the valid codeword count meets or exceeds the number of codewords required to fill the destination block stripe, go to step 210]), including a respective first block stripe in the set of source block stripes and incrementing the valid codeword count by a number of valid codewords in the respective first block stripe (Wei, [0047 - Following step 210, go to step 214 where the processing device determines whether to use an aggressive GC policy. Since Yes, the GC process selects a candidate block stripe for processing and folding into a target/destination block stripe, thereby including a respective first block stripe in the set of source block stripes. Step 210 is followed by steps 214,218,220,224:No, and back to step 202 to include the next first stripe into the set of source block stripes. As per Para-0016, the GC procedure uses a valid page/VP bitmap that tracks valid translation units for each block stripe, and Para-0039 recites that a P2L table determines valid translation units in the candidate block stripe. These citations imply incrementing the valid codeword count by a number of valid codewords in the respective first block stripe; Since neither the spec nor the claim recite how the incrementing is achieved, the citation is a valid interpretation]).
Neither the claim nor the spec define a ‘valid codeword count’ and how it is determined.
Manning discloses,
maintaining a valid (Manning, [0045 – In Fig. 3, LP5 and LP7 as good physical pages of memory, can be populated with error data that can be used to maintain the RAIN stripe, e.g., so that parity data can be calculated and be valid for the RAIN stripe]) codeword count (Manning, [0058 - Fig. 6 shows a GC/wear leveling operation]; [0024 – In Fig. 1, a codeword can have a total size that includes a wrapper/parity and a payload/data]; [0013 - Error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory]; [0027 – In Fig. 1, controller 108 is configured to error code a portion of a number of logical pages of data as a number of codewords/valid codeword count]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the valid number of codewords of Manning into the optimized GC process of Wei, Sharon, Ohno for the benefit of the controller being configured to error code a portion of a number of logical pages of data as a number of codewords by error coding the portion of the number of logical pages of data as the number of codewords each having a payload size equal to a size of each of a number of logical buffer segments (Manning, 0027).
As per Claim 12, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 19, it is similar to claim 4 and therefore the same mappings are incorporated.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Schneider et al.(20200034229) involves a processing device for selecting a first prime number for computing parity blocks for a first stripe and a first number of sub-stripes for splitting stripe columns of the first stripe on storage devices according to compress block size. The processing device generates the first stripe and metadata according to the first compress block size, first prime number and first sub-stripes number. The processing device stores compressed data in the first stripe according to the compress block size. The processing device stores first prime number and second number sub-stripes on a storage system(Schneider, abstract).
Walsh et al.(11550658) involves a controller for storing first and second codewords in a volatile memory i.e. RAM, where the first and second codewords comprise a data payload and an error correction code generated from the data payload, the data payload of the first codeword comprises a first logical-to-physical address table entry read from a non-volatile memory (NVM) (104) and a portion of a second logical-to-physical address table entry read from the non-volatile memory, and data payload of the second codeword comprises a remainder of the second logical-to-physical address table entry, and the NVM comprises a three-dimensional memory(Walsh, abstract).
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights