Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant's filing on 25 July 2025. Claims 1-22 are presently pending and under consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, 10-13, 17, 20-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Um (US 2021/0224187 A1, hereinafter Um).
Regarding claims 1, 11, and 21, taking claim 1 as exemplary, Um discloses a memory system (See Um, Fig. 1 and [0021], “Fig. 1 illustrates a memory system”), comprising:
one or more memory devices (See Um, [0036], “the memory device 150 may include a first memory die (DIE0) 1501 and a second memory die (DIE1) 1502”); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system (See Um, [0021] “the memory system includes a controller 130 and a memory device 150. The controller 130 cooperates with a host 102 and the memory device 150. The controller 130 may include a host interface (I/F) 132, flash translation layer (FTL) circuitry 40, a memory interface (I/F) 142, and a memory 144”) to:
receive signaling indicating a state of one or more logical memory addresses, the state comprising one of a valid state or an invalid state (See Um [0025] “the host request manager 46 may use the map manager 44 and the block manager 48 to handle or process requests according to the read and program commands, and events which are delivered from the host interface 132. The host request manager 46 may send an inquiry or request to the map data manager 44, to determine a physical address corresponding to the logical address which is entered with the events” and [0028] “to determine validity of each page, the state manager 42 may identify a logical address “stored in an out-of-band (OOB) area of each page. To determine whether each page is valid or not”);
determine whether a state of a first logical memory address of the one or more logical memory addresses comprises the valid state or the invalid state in response to the signaling (See Um [0028] “to determine validity of each page, the state manager 42 may identify a logical address “stored in an out-of-band (OOB) area of each page. To determine whether each page is valid or not, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the request. The state manager 42 sends a program request to the block manager 48 for each valid page”);
adjust a counter allocated to a memory region corresponding to the first logical memory address in response to determining that the state of the first logical memory address comprises the valid state (See Um, [0073], disclosing a valid page count of each source block used for victim block selection and [0075] disclosing validity on page basis, which necessarily requires adjusting the counter based on validity state of the addresses/pages which are the basis of the block); and
perform a garbage collection operation in accordance with a value of the counter (See Um [0074] “[0074] In the present embodiment, a victim block is selected using the first method, e.g., based on a valid page count (VPC) of each source block and the predetermined second threshold value TH2. For example, referring to FIG. 5, when the garbage collection module 196 enters the garbage collection mode and the second threshold value TH2 for selecting a victim block is set to ‘30,’ the zeroth block BLK0 may be selected as a victim block since the valid page count of the zeroth block BLK0 is 25, the valid page count of the first block BLK1 is 50, and the valid page count of the second block BLK2 is 66”).
Regarding claims 2, 12, and 22, taking claim 2 as exemplary, Um disclosed the memory system of claim 1 as above. Um further discloses wherein the processing circuitry is further configured to cause the memory system to: receive second signaling indicating whether data stored at one or more physical memory addresses of the memory system comprises valid data or invalid data (See Um, [0028] “To determine whether each page is valid or not, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the request”).
Regarding claims 3 and 13, taking claim 3 as exemplary, Um disclosed the memory system of claim 2 as above. Um further discloses wherein the processing circuitry is further configured to cause the memory system to: determine whether valid data or invalid data is stored at a first physical memory address of the one or more physical memory addresses corresponding to the first logical memory address (See Um, [0028] “To determine whether each page is valid or not, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the request”),
wherein adjusting the counter is in response to determining that valid data is stored at the first physical memory address (See Um, [0028] “To determine whether each page is valid or not, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the request” and [0073], disclosing a valid page count of each source block used for victim block selection and [0075] disclosing validity on page basis, which necessarily requires adjusting the counter based on validity state of the addresses/pages which comprise the block).
Regarding claims 7 and 17, taking claim 7 as exemplary, Um disclosed the memory system of claim 1 as above. Um further discloses wherein receiving the signaling indicating the state of the one or more logical memory addresses comprises the processing circuitry configured to cause the memory system to: receive a command that indicates the state of the one or more logical memory addresses (See Um, [0028] “to determine validity of each page, the state manager 42 may identify a logical address stored in an out-of-band (OOB) area of each page. To determine whether each page is valid or not, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the request. The state manager 42 sends a program request to the block manager 48 for each valid page. A mapping table may be updated through the update of the map manager 44 when the program operation is complete”).
Regarding claims 10 and 20, taking claim 10 as exemplary, Um disclosed the memory system of claim 9 as above. Um further discloses wherein performing the garbage collection operation comprises the processing circuitry configured to cause the memory system to: select the second memory region as a source of the garbage collection operation in response to a value of the second counter being smaller than a value of the counter (See Um, [0074] “[0074] In the present embodiment, a victim block is selected using the first method, e.g., based on a valid page count (VPC) of each source block and the predetermined second threshold value TH2. For example, referring to FIG. 5, when the garbage collection module 196 enters the garbage collection mode and the second threshold value TH2 for selecting a victim block is set to ‘30,’ the zeroth block BLK0 may be selected as a victim block since the valid page count of the zeroth block BLK0 is 25, the valid page count of the first block BLK1 is 50, and the valid page count of the second block BLK2 is 66”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 9, 16, and 19 are rejected under 35 U.S.C. 103 as being anticipated by Um (US 2021/0224187 A1, hereinafter Um).
Regarding claims 6 and 16, taking claim 6 as exemplary, Um disclosed the memory system of claim 1 as above. Um further discloses wherein the processing circuitry is further configured to cause the memory system to: receive, after receiving the signaling, second signaling indicating a second state of the one or more logical memory addresses, the second state comprising one of the valid state or the invalid state (Repeating the process of Um disclosed at [0025] and which discloses a plurality of read and program command requests, “the host request manager 46 may use the map manager 44 and the block manager 48 to handle or process requests according to the read and program commands, and events which are delivered from the host interface 132. The host request manager 46 may send an inquiry or request to the map data manager 44, to determine a physical address corresponding to the logical address which is entered with the events” and [0028] “to determine validity of each page, the state manager 42 may identify a logical address “stored in an out-of-band (OOB) area of each page. To determine whether each page is valid or not”, or in other words, receive a second read/write command to the same logical address); and
compare the state of the one or more logical memory addresses to the second state of the one or more logical memory addresses in response to receiving the second signaling (See Um, [0028] “To determine whether each page is valid or not, the state manager 42 may compare the physical address of the page with the physical address mapped to the logical address obtained from the request”, in which the validity/invalidity of the data at the logical address is “compared” with the assumed “valid” data of second read/write command as the validity may have changed due to the first command/signaling).
While Um does not disclose the repeat of the validity determination process, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to repeat the validity determination process disclosed by Um at [0025] & [0028] as memory system useability would be increased by allowing the system to handle more than a single host command request and more than a single logical/physical address.
Regarding claims 9 and 19, taking claim 9 as exemplary, Um disclosed the memory system of claim 1 as above. Um further discloses wherein the processing circuitry is further configured to cause the memory system to: determine whether a state of a second logical memory address of the one or more logical memory addresses comprises the valid state or the invalid state in response to the signaling (Repeating the process disclosed by Um at [0025] and which discloses a plurality of read and program command requests, “the host request manager 46 may use the map manager 44 and the block manager 48 to handle or process requests according to the read and program commands, and events which are delivered from the host interface 132. The host request manager 46 may send an inquiry or request to the map data manager 44, to determine a physical address corresponding to the logical address which is entered with the events” and [0028] “to determine validity of each page, the state manager 42 may identify a logical address “stored in an out-of-band (OOB) area of each page. To determine whether each page is valid or not”); and
adjust a second counter allocated to a second memory region corresponding to the second logical memory address in response to determining that the state of the second logical memory address comprises the valid state (See Um, [0073], disclosing a valid page count of each source block used for victim block selection and [0075] disclosing validity on page basis, which necessarily requires adjusting the counter based on validity state of the addresses/pages which are the basis of the block, where a second block has its own corresponding valid page counter in order for source block valid page counts to be compared).
While Um does not disclose the repeat of the validity determination process and the use of a second counter, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to repeat the validity determination process disclosed by Um at [0025] & [0028] as memory system useability would be increased by allowing the system to handle more than a single host command request and more than a single logical/physical address and the use of a second counter to count is merely a duplication of parts and which has been to have no patentable significance unless a new and unexpected result is produced (See MPEP 2144.04).
Claims 4, 5, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Um (US 2021/0224187 A1, hereinafter Um) in view of Thompson et al (US 2018/0260319 A1, hereinafter Thompson).
Regarding claims 4 and 14, taking claim 4 as exemplary, Um disclosed the memory system of claim 1 as above. Um does not disclose wherein receiving the signaling indicating the state of the one or more logical memory addresses comprises the processing circuitry configured to cause the memory system to: receive a command comprising an extra header segment that indicates the state of the one or more logical memory addresses.
However, Thompson discloses wherein receiving the signaling indicating the state of the one or more logical memory addresses comprises the processing circuitry configured to cause the memory system to: receive a command comprising an extra header segment that indicates the state of the one or more logical memory addresses (See Thompson, [0006] “appending a header to each segment of system data before writing the system data to the one or more blocks of the NAND flash memory devices. In one embodiment, the header includes at least one of a logical address associated with a segment of user or system data, a timestamp, and a valid bitmap status” [0040] & [0041] “FIG. 3A shows a segment of user data stored on a NAND flash memory device, according to one embodiment of the invention. The segment of user data has a header 320 including information about the segment of user data” & “In another embodiment, the header 320 includes a timestamp. In another embodiment, the header 320 includes a valid bitmap status”).
Um and Thompson are analogous art directed to improved flash management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the improved garbage collection system of Um with the combined header data of Thompson as memory system management performance can be increased by removing the need for a distinct NAND flash region for storying system management data (See Thompson, [0035], “the memory controller does not need to set aside a distinct area on the NAND flash memory for system data storage because the system data 213a-c is stored in the same format as user data 210a-d on a blended data block containing both user and system data”).
Regarding claims 5 and 15, taking claim 5 as exemplary, Um in view of Thompson disclosed the memory system of claim 4 as above. Um further discloses wherein the command comprises a write command, a read command, or a garbage collection command (See Um, [0025] “the host request manager 46 may use the map manager 44 and the block manager 48 to handle or process requests according to the read and program commands, and events which are delivered from the host interface 132”).
Allowable Subject Matter
Claims 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Um discloses a memory system using a counter to track validity of logical memory addresses and perform garbage collection based on the value of the counter.
Thompson discloses the use an appended header to segment data to store additional information such as system data, validity data and timestamp information.
Lee (US 20210191857 A1) discloses performing background garbage collection when the device is in an idle state or in a sleep state.
Lin (US 2022/0317878 A1) discloses based on receipt of a deallocate command from a host device, a flash memory controller updating a valid page count table, a detailed valid page count table and/or a zone valid page count table according to the deallocate command and determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.
However, the prior art alone or in combination fails to teach or fairly suggest the combination of:
the processing circuitry configured to cause the memory system to: enter, prior to determining whether the state of the first logical memory address of the one or more logical memory addresses comprises the valid state or the invalid state, a sleep mode, wherein adjusting the counter occurs while the memory system is in the sleep mode.
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDMUND H KWONG whose telephone number is (571)272-8691. The examiner can normally be reached Monday-Friday 10-6 PT.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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