Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Application is a continuation of and claims the benefit of and priority to U.S. Application No. 18/187,092, filed March 21, 2023, now patent 12430263, which is a continuation of and claims the benefit of and priority to U.S. Application No. 16/973,998, filed December 10, 2020, now issued as U.S. Patent Number 11,615,034, which under 35 U.S.C. § 371, claims the benefit of and priority to International Application No. PCT/CN2018/108215, filed September 28, 2018.
Claims 1-12 are pending for examination in response to preliminary amendment filed on 10/20/2025.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/18/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir.1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington,418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visithttp://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.jsp.
Claim 1 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 11,615,034 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the differences between claim 1 of instant application and claims 1 of patent application are not sufficient to render the claim patentably distinct and therefore a terminal disclaimer is required.
The following table only compares claim 1 of instant application to patent 11,615,034 B2. However, the depended claims are rejected since they are depended on the rejected claim 1 and they are similar to the dependent claims of patent applications.
Instant application 19/282889
Patent 11,615,034 B2
A method comprising:
A computer implemented method, comprising:
reserving, by processing circuitry of a computing device, a block of physical memory communicatively coupled to the processing circuitry;
reserving a block of physical memory communicatively coupled to a processor;
allocating a first portion of the block of physical memory for use with one or more processes executing on the processing circuitry, the first portion configured as a single memory page having a first page size; and
allocating a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size;
generating an entry in a transaction lookaside buffer (TLB) entry for the single memory page, the TLB entry comprising a physical page number (PPN), a tag, an extensible page size indicator (ESI) field, and an actual page size indicator (ASI) field; and
in response to a determination that an amount of physical memory required by the one or more processes executing on the processing circuitry exceeds a first threshold:
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold:
allocating additional memory to the first portion of the block of physical memory; and increasing the single memory page from a first page size to a second page size.
allocating additional memory to the first portion of the block of physical memory; and increasing the single memory page from a first page size to a second page size.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by van Riel et al., US 2017/0075814 A1.
Regarding claims 1, 5 and 9, van Riel teaches a method, comprising:
Reserving, by processing circuitry of a computing device, a block of physical memory communicatively coupled to the processing circuitry (section 0024; Each page entry corresponds to a memory page or a sub-page of a memory page. For example, the page entry 106 includes parameters that define a memory page or sub-page; the page entry 106 may also be used to determine a page frame number, which may identify a physical address of the memory page in the memory);
allocating a first portion of the block of physical memory for use with one or more processes executing on the processing circuitry (see abstract and Fig.3A and section 000043-0044; receive request to allocate memory and response to the request, the kernel determines whether to allocate a page or sub-page based on the size of the memory that is requested to be allocated), the first portion configured as a single memory page having a first page size (section 0044-0045 and section 0050; it is taught as allocate sub-page); and
in response to a determination that an amount of physical memory required by the one or more processes executing on the processing circuitry exceeds a first threshold (see abstract and section 0044-0045; section 0047 and 0049; the size threshold may be pre-configured or user-defined. For example, a pre-configured size threshold may be set to the size of a sub-page; At action 306, based upon the comparison, the kernel determines that the page should be allocated (rather than a sub-page). Thus, a page is allocated and initialized:
allocating additional memory to the first portion of the block of physical memory (section 0051 and section 0057; If the requested memory is larger than the sub-page, additional memory sub-pages may also be initialized); and
increasing the single memory page from a first page size to a second page size (section 0057; the sub-page entry corresponding to the sub-page is initialized in a same page array that is used to store page entries of pages; the sub-page entry is stored within the memory page that includes the sub-page, such as within the sub-page itself as is illustrated in FIG. 2).
For claim 9, van Riel also teaches a memory communicatively coupled to the processing circuitry (Fig.6 and section 0109; a memory can be considered as a data storage device).
Regarding claims 2, 6 and 10, van Riel teaches further comprising: implementing a single addressing scheme for the first portion of the block of physical memory (Fig.5A and section 0091; Each page/sub-page in memory has a page frame number that identifies the physical address of the page/sub-page in the memory and offsets that identify locations within the page/sub-page), wherein the processing circuitry is coupled to a memory, the processing circuitry having graphics processing circuitry (section 0042-0043; section 0069-0070 and section 0105-0106).
Regarding claims 3, 7 and 11, van Riel teaches the first page size is 4KB (section 0052; the sub-page is 4KB); and the second page size is 8KB (the second page can be two sub-page which is 8KB).
Regarding claims 4, 8 and 12, van Riel teaches further comprising: in response to a determination that an amount of physical memory required by the one or more processes executing on the processing circuitry exceeds a second threshold: allocating additional memory to the first portion of the block of physical memory; and increasing the single memory page from a second page size to a third page size (section 0048- 049; the kernel may calculate whether more than a threshold number of sub-pages would be allocated to fit the size of the memory requested based upon the comparison, the kernel determines that the page should be allocated (rather than a sub-page). Thus, a page is allocated and initialized; allocating a page includes updating or adding a page entry in a page array and indexing the page entry within the page array).
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133
