DETAILED ACTION
The current Office Action is in response to the papers submitted 10/29/2025. Claims 21 - 40 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21 - 40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 12 of U.S. Patent No. 12379855 and claims *** of U.S. Patent No. 11947810. Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons listed below.
Instant Application
Pat 12379855
Reasoning
21. A method of operating a semiconductor memory device connected to a memory controller through a link, the semiconductor memory device including a memory cell array including a plurality of volatile memory cells and a cyclic redundancy check (CRC) engine, the method comprising: receiving, from the memory controller through the link, main data and system parity data; detecting an error associated with at least one of the main data or the system parity data; generating an error flag indicating that the error corresponds to at least one of a first type of error associated with the link or a second type of error associated with the volatile memory cells; and transmitting the error flag to the memory controller.
1. A method of operating a semiconductor memory device that includes a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines and a cyclic redundancy check (CRC) engine, the method comprising: detecting, by the CRC engine, an error in a main data and a system parity data received from a memory controller through a link, the memory controller being external to the semiconductor memory device; generating, by the CRC engine, an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and transmitting, by the CRC engine, the error flag to the memory controller.
Both claims disclose the same method of used between a memory device including a memory cell array and coupled to a memory controller. The methods both disclose receiving main data and parity data from the controller, detecting an error in the main data and/or parity data, generating an error flag based on the error detection, and transmitting the error flag to the memory controller.
The instant application discloses detecting an error in the main data or the parity data while Pat 12379855 discloses detecting an error in the main data and the parity data. The scope of the instant application using the “or” limitation is considered to cover the scope of the “and” limitation since there is no indication in the instant application that the error is detected in only one of the main data or the parity data. The instant application covers detecting an error in either location which includes detecting an error in both locations.
22
1 and 2
The generating and determining steps are the same and Pat 12379855 discloses a write operation based on a write command from the memory controller. The instant application discloses receiving a write command and initiating a write operation based on the received write command where the main data and parity data are received in response to the initiated write operation. Claim 1 of Pat 12379855 discloses receiving the main data and parity data which is a write command that includes the main data and parity data.
23
3
Both claims disclose the same method steps
24
4
Both claims disclose the same method steps
25
5
Both claims disclose the same method steps
26
6
Both claims disclose the same method steps
27
7
Both claims disclose the same method steps
28
8
Both claims disclose the same method steps
29
9
Both claims disclose the same method steps
30
10
Both claims disclose the same method steps
31
11
Both claims disclose the same method steps
32
12
Both claims disclose the same method steps
33
1
Similar reasoning used with regard to claim 21 above. Claim 33 is a device claim and claim 1 is a method claim. Both claims disclose the same hardware and process/method of using the hardware.
34
1 and 2
Same reasoning used regarding claim 22 above.
35
3
Same reasoning used regarding claim 23 above
36
4
Same reasoning used regarding claim 24 above
37
5
Same reasoning used regarding claim 25
38
6
Same reasoning used regarding claim 26 above
39
11
Same reasoning used regarding claim 31 above
40
12
Same reasoning used regarding claim 32 above
The claims in Pat 12379855 were deemed as being double patenting to the claims in Pat 11947810 on 09/11/2024. Since the instant application is double patenting with Pat 12379855 this shows the instant application is also considered double patenting with Pat 11947810 for similar reasons indicated above since Pat 12379855 and Pat 11947810 are double patenting with each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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