DETAILED ACTION
It would be of great assistance to the Office if all incoming papers pertaining to a filed application carried the following items:
1. Application number (checked for accuracy, including series code and serial no.).
2. Group art unit number (copied from most recent Office communication).
3. Filing date.
4. Name of the examiner who prepared the most recent Office action.
5. Title of invention.
6. Confirmation number (See MPEP § 503).
Status of Claims
Claims 1, 7 and 8 have been amended, new claims 11 and 12 have been added, and claims 1 – 12 are now pending.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 12 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
As to claim 12, the specification as originally filed does not provide support for the recitation of the claim “gate driving units includes a low level block, an emission block, a scan1 block and a scan2 block, wherein a low level power line, a first contact electrode and a second contact electrode are disposed in the low level block, wherein a bank layer is disposed between the second planarizing layer and a second electrode of the light emitting diode, and wherein the second electrode is connected to the second contact electrode through an opening in the bank layer, the second contact electrode is connected to the first contact electrode through a contact hole in the second planarizing layer, and the first contact electrode is connected to the low level power line through a contact hole in the first planarizing layer”. The specification as first filed does not reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention “gate driving units includes a low level block, an emission block, a scan1 block and a scan2 block, wherein a low level power line, a first contact electrode and a second contact electrode are disposed in the low level block, wherein a bank layer is disposed between the second planarizing layer and a second electrode of the light emitting diode, and wherein the second electrode is connected to the second contact electrode through an opening in the bank layer, the second contact electrode is connected to the first contact electrode through a contact hole in the second planarizing layer, and the first contact electrode is connected to the low level power line through a contact hole in the first planarizing layer”. Particularly, the specification fails to disclose a low level block, an emission block, a scan1 block and a scan2 block, their location or function, the specification further fails to disclose the specific interconnection as recited in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4 – 8 and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ishii (US 2025/0329293).
As to claim 1, Ishii discloses a display device, comprising:
a display panel (display panel 100 of fig. 1) having a display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13) and a non-display area (area outside the area occupied by light-emitting elements 210 of fig. 1) at a periphery of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13);
first and second gate driving units (left and right scan-line driver circuits 110 of fig. 1) in edge portions of the display area (left and right edges of area occupied by light-emitting elements 210 of fig. 1);
a plurality of circuit parts (pixel circuits 130 of fig. 5 and 13) in a central portion of the display area between the edge portions (between gate drivers as shown in fig. 5 [0040]) and connected to the first and second gate driving units (left and right scan-line driver circuits 110 of fig. 1);
and a plurality of emission parts (light-emitting element 210 of fig. 1 and 13) above the first and second gate driving units (left and right scan-line driver circuits 110 of fig. 1) and the plurality of circuit parts (pixel circuits 130 of fig. 5 and 13) and connected to the plurality of circuit parts (light-emitting element 210 are connected to the pixel circuits 130 of fig. 5 and 13),
wherein at least one of the plurality of circuit parts (pixel circuits 130 of figs. 5, 9, 10 and 13) includes at least one transistor (160 of figs. 8 – 10),
wherein at least one of the plurality of emission parts (light-emitting element 210 of fig. 1 and 13 connected to wiring 154 of fig. 9) includes a light emitting diode (210 of fig. 8), wherein the at least one transistor (160 of figs. 8 – 10) is connected to the light emitting diode (210 of fig. 8) through a connecting electrode (connection at node n of fig. 8, shown as connection wiring between 160 and 172 of fig. 9),
wherein a first planarizing layer (leveling film 200 of fig. 10) is disposed on the at least one transistor (160 of fig. 10), and
wherein the connecting electrode (connection wiring between 160 and 172 of fig. 9) is connected directly to a drain electrode of the at least one transistor (direct connection to the drain of 16 of fig. 9 [shown below]).
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As to claim 4 (dependent on 1), Ishii discloses the display device, wherein
the plurality of circuit parts (pixel circuits 130 of fig. 5 and 13) include first (130-1 of fig. 13), second (130-2 of fig. 13) and third circuit parts (130-3 of fig. 13), wherein
the plurality of emission parts (light-emitting element 210 of fig. 1 and 13) include first (210-1 of fig. 13), second (210-2 of fig. 13) and third (210-3 of fig. 13) emission parts (light-emitting element 210 of fig. 1 and 13), wherein
the first (130-1 of fig. 13), second (130-2 of fig. 13) and third circuit parts (130-3 of fig. 13) are sequentially and repeatedly disposed in the central portion (figs.2, 5 and 13) of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13), and wherein
the first (210-1 of fig. 13), second (210-2 of fig. 13) and third (210-3 of fig. 13) emission parts (light-emitting element 210 of fig. 1 and 13) are sequentially and repeatedly disposed (figs. 2, 5 and 13) throughout an entirety of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13).
As to claim 5 (dependent on 4), Ishii discloses the display device, wherein
an overall width of the first (130-1 of fig. 13), second (130-2 of fig. 13) and third circuit parts (130-3 of fig. 13) is smaller (fig. 13) than an overall width of the first (210-1 of fig. 13), second (210-2 of fig. 13) and third (210-3 of fig. 13) emission parts (light-emitting element 210 of fig. 1 and 13).
As to claim 6 (dependent on 4), Ishii discloses the display device, wherein
the first (130-1 of fig. 13), second (130-2 of fig. 13) and third circuit parts (130-3 of fig. 13) of the central portion of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13) are connected to the first (210-1 of fig. 13), second (210-2 of fig. 13) and third (210-3 of fig. 13) emission parts (light-emitting element 210 of fig. 1 and 13), respectively (fig. 13), of the entirety of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13) through a connecting electrode (relay wiring 154 of fig. 13).
As to claim 7 (dependent on 4), Ishii discloses the display device, wherein
each of first (130-1 of fig. 13), second (130-2 of fig. 13) and third circuit parts (130-3 of fig. 13) includes at least one transistor (transistor 160 of fig. 8), wherein
each of the firs first (210-1 of fig. 13), second (210-2 of fig. 13) and third (210-3 of fig. 13) emission parts (light-emitting element 210 of fig. 1 and 13)includes a light emitting diode (diode 210 of fig. 8), and wherein
the at least one transistor (160 of fig. 8) is connected to the light emitting diode (210 of fig. 8) through a connecting electrode (154 of fig. 8).
As to claim 8 (dependent on 7), Ishii discloses the display device, wherein
a first planarizing layer (leveling film 200 of fig. 10) is disposed on the at least one transistor (160 of fig. 10), wherein
the connecting electrode (154 of fig. 10) is connected to the at least one transistor (160 of fig. 10) through a contact hole (198 of fig. 10) in the first planarizing layer (leveling film 200 of fig. 10), wherein
a second planarizing layer (fourth leveling film 202 of fig. 10) is disposed on the connecting electrode (154 of fig. 10), wherein
the light emitting diode (210 of fig. 10) is disposed on the second planarizing layer (fourth leveling film 202 of fig. 10), and wherein
the light emitting diode (210 of fig. 10) is connected to the connecting electrode (154 of fig. 10) through a contact hole (area of electrode 212 of fig. 10) in the second planarizing layer (fourth leveling film 202 of fig. 10).
As to claim 11 (dependent on 1), Ishii discloses the display device, wherein the at least one transistor includes a semiconductor layer (180 of fig. 10), a gate electrode (184 of fig. 10), a source electrode and a drain electrode (source and drain of 160 shown in fig. 9), wherein a gate insulating layer (182 of fig. 10) is disposed between the semiconductor layer (180 of fig. 10) and the gate electrode (184 of fig. 10), and first and second interlayer insulating layers (192 and 200 of fig. 10) are disposed between the gate electrode and the source electrode and between the gate electrode and the drain electrode (as shown in figs. 9 and 10), wherein a first capacitor electrode (first capacitance electrode 188 of the storage capacitance element 174 of fig. 10) is disposed between the gate insulating layer (182 of fig. 10) and the first interlayer insulating layer (192 of fig. 10), and a second capacitor electrode (196 of fig. 10) is disposed between the first interlayer insulating layer (192 of fig. 10) and the second interlayer insulating layer (200 of fig. 10), and wherein the first capacitor electrode (188 of fig. 10), the first interlayer insulating layer (192 of fig. 10) and the second capacitor electrode (196 of fig. 10) constitute a storage capacitor (174 of fig. 9 -10 [0050]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii.
As to claim 2 (dependent on 1), Ishii discloses the display device, wherein the plurality of emission parts (light-emitting element 210 of fig. 1 and 13) are arranged by being shifted by different shift values along each of left directions (fig. 13 [0055]) from a region directly above the plurality of circuit parts connected thereto (pixel circuits 130 of fig. 5 and 13), but does not explicitly disclose shift in the right direction. However, Ishii discloses the display device symmetric along vertical central axis (fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ishii such the plurality of emission parts were arranged by being shifted by different shift values along each of left and right directions, with motivation to provide symmetric display, wherein such modification would have simply required a routine skill.
As to claim 3 (dependent on 1), Ishii discloses the display device, wherein the plurality of emission parts (light-emitting element 210 of fig. 1 and 13) are arranged by being shifted by different shift values along left directions (fig. 13 [0055]) from a region directly above the plurality of circuit parts connected thereto (pixel circuits 130 of fig. 5 and 13), and the shift values gradually increase (fig. 13 [0055]) to left end lines of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13, inherently the shift is mirrored about center line); and/or the plurality of circuit parts (pixel circuits 130 of fig. 5 and 13) and the plurality of emission parts (light-emitting element 210 of fig. 1 and 13) have the same number as each other (fig. 13), but does not explicitly disclose shift in the right direction, or that the shift is from a central line of the display area (area occupied by light-emitting elements 210 of figs. 1, 3 and 13). However, Ishii discloses the display device symmetric along vertical central axis (fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ishii such the plurality of emission parts were arranged by being shifted by different shift values along each of left and right directions and centered around central line, with motivation to provide symmetric display, wherein such modification would have simply required a routine skill.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Park et al. (US 2021/0327361).
As to claim 9 (dependent on 1) and claim 10 (dependent on 9), Ishii discloses the display device, wherein the first and second gate driving units (left and right scan-line driver circuits 110 of fig. 1) generate a gate signal and supply the gate signal to the plurality of circuit parts (pixel circuits 130 of fig. 5 and 13), the display device, further comprising: a data driving unit that generates a data signal (signal-line driver circuit 112 of fig. 1) and supplying the data signal to the plurality of circuit parts (pixel circuits 130 of fig. 5 and 13); but does not explicitly disclose generating the gate signal using a gate control signal, generating the data signal using an image data and a data control signal; and a timing controlling unit that generates the image data, the data control signal and the gate control signal using an image signal and a timing signal, the timing controlling unit transmitting the image data and the data control signal to the data driving unit and transmitting the gate control signal to the first and second gate driving units.
In the same filed of endeavor, Park discloses a display device, wherein: generating the gate signal using a gate control signal (control signal to the scan drivers from the timing controller 10 of fig. 1 [0051]), generating the data signal using an image data and a data control signal, the device comprising (gray scale values signal and control signal to the data driver from the timing controller 10 of fig. 1 [0051]), the device comprises: a timing controlling unit (10 of fig. 1) that generates the image data (grayscale values [0051]), the data control signal (data control signal [0051]) and the gate control signal (gate control signal [0051]) using an image signal (RGB signal [0051]) and a timing signal (data enable signal [0051]), the timing controlling unit transmitting the image data and the data control signal to the data driving unit and transmitting the gate control signal to the first and second gate driving units (The timing controller 10 may generate control signals to be supplied to the data driver 20, the first scan driver 30, the second scan driver 40, and the like based on the external input signal to correspond to the specifications of the display device 9 [0051]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishii and the teachings of Park such that the timing controller was provided as disclosed by Park, with motivation to provide necessary signal for displaying image wherein such modification would have only required a routine skill.
Response to Arguments
Applicant's arguments filed 08/10/2026 have been fully considered but they are not persuasive.
As to Applicant’s argument that Ishii fails to disclose elements of newly amended claim 11, the Examiner respectfully disagrees. Ishii discloses that at least one of the plurality of circuit parts (pixel circuits 130 of figs. 5, 9, 10 and 13) includes at least one transistor (160 of figs. 8 – 10), wherein at least one of the plurality of emission parts (light-emitting element 210 of fig. 1 and 13 connected to wiring 154 of fig. 9) includes a light emitting diode (210 of fig. 8), wherein the at least one transistor (160 of figs. 8 – 10) is connected to the light emitting diode (210 of fig. 8) through a connecting electrode (connection at node n of fig. 8, shown as connection wiring between 160 and 172 of fig. 9), wherein a first planarizing layer (leveling film 200 of fig. 10) is disposed on the at least one transistor (160 of fig. 10), and wherein the connecting electrode (connection wiring between 160 and 172 of fig. 9) is connected directly to a drain electrode of the at least one transistor (direct connection to the drain of 16 of fig. 9 [shown above]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY BOLOTIN whose telephone number is (571)270-5873. The examiner can normally be reached M-F 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY BOLOTIN/Primary Examiner, Art Unit 2623
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