DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 10/8/24. It is noted, however, that applicant has not filed a certified copy of the 10-2024-0136582 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 5 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dally et al. U.S. Pat. App. Pub. No. 2006/0165185 (cited by Applicant).
Regarding claim 5, Dally discloses a switched capacitor equalizer (see Figs. 2, 7, 9) comprising: a first integrating amplifier (M36 – Fig. 7), of which one end is connected to an input node (rclk2P) and of which the other end is connected to a first output node (OutP1); a second integrating amplifier (M37) of which one end is connected to the input node (rclk2P) and of which the other end is connected to a second output node (OutN1); a coupling capacitor (C1), of which one end is connected to the first output node (OutP1) and of which the other end is connected to the second output node (OutN1); a first transistor (M30), of which one end is connected to a power supply (VbiasN through node 74, M29) and of which the other end is connected to the first output node (through M31, M36); and a second transistor (M33) of which one end is connected to a power supply (VbiasN through node 74, M29) and of which the other end is connected to the first output node (through M34, M37).
Regarding claim 10, Dally further discloses a reset timing controller (clock recovery 109 – Fig. 9) connected to the first and second transistors and configured to control timing (¶ [0070]).
Allowable Subject Matter
Claims 1-4 are allowed.
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hochschild et al. U.S. Pat. No. 4,862,121 disclose a switched capacitor equalization filter.
Zerbe U.S. Pat. No. 6,396,329 discloses an equalizer in a receiver comprising integrating amplifiers.
Bulzacchelli et al. U.S. Pat. App. Pub. No. 2008/0187037 disclose an equalizer employing integrating summing amplifiers producing odd and even data outputs based on respective clock periods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David B. Lugo whose telephone number is 571-272-3043. The examiner can normally be reached M-F, 9-6.
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/DAVID B LUGO/Primary Examiner, Art Unit 2631 9/30/2026
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