DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Other Refs:
Ahn (US 20200151106) , the non-volatile memory including a memory cell array, the memory cell array including a first plane and a second plane, the method includes receiving a read command set for data sensing of the first and second plane; relevant to claimed nonvolatile memory.. plurality of planes… receive commands … target plane.
Non-patent Literature – Cheong, Wooseong (A flash memory controller for 15us ultra-low-latency SSD using high speed 3B NAND flash with 3 us read time), published 2018 IEEE International Solid-State Circuits Conference (ISSCC), 2018 – relevant to claimed nonvolatile memory receiving commands, input/output … control logic circuit configured to… detect read command … time has elapsed.
In order to potentially overcome the rejections (subject to the original disclosure), the Office suggest amending the claims to clarify the limitations related to: “fixed-time read” (Claims 1, 13, 17); order in which… received.. and restored… are consistent (Claim 13); and schedule fixed-time read commands.. interleave the fixed-time read commands .. in parallel (Claim 17).
In order to overcome this office action for allowance, the Office suggest amending the claims to including allowable subject matter (as indicated below).
Oath filed 7/30/2025 is placed in file.
Allowable Subject Matter
Claims 3, 11 and/or 12 objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
For Claims 3, 11 and 12 the prior art discloses and/or renders obvious the limitations from Claims 1. The prior art does not appear to disclose the limitations from Claims 11 and 12 when viewed in combination with their respective base claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,4,5,6,7,8 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Wakchaure (US 20190227749) and further in view of Ishii (US 20180246660)
Claim 1. Palmer discloses A nonvolatile memory (eg., 0038 – Fig. 2 - 3D NAND architecture semiconductor memory array 200), comprising:
a plurality of planes (eg., 0040 - NAND memory device can include, 548 blocks per plane, and 4 or more planes per device),
each plane of the plurality of planes including a plurality of word lines (eg., 0041 - word lines (WL) WL0.sub.0-WL7.sub.0 210A-217A, WL0.sub.1-WL7.sub.1 210B-217B, etc.),
a plurality of bit lines (eg., 0039 - bit lines (BL) BL0-BL2 220-222)), and
a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines, wherein the plurality of memory cells are multi-level cells (eg., 0038 Fig. 2 - strings of memory cells (e.g., first-third A.sub.0 memory strings 205A.sub.0-207A.sub.0, );
an input/output controller configured to receive commands and addresses through a channel, input/output data through the channel (eg., 0057 Fig. 4 - input/output (I/O) circuit 426 can transfer values of data in or out of the memory device 400), and
detect a fixed-time read command ; a status delay logic configured to and based on an address received with the fixed-time read command, and determine a delay time based on (eg., 0062 Fig. 5 - Multiplane read compatible read commands are two read commands targeting two different portions of a same memory (e.g., NAND) die. Rather than immediately issue the first read request, the memory controller delays issuing the read command to the memory array until the earliest of the expiry of the delay time period or the receipt of a multiplane read compatible read command (e.g., a second read request to a second portion of the first die)) .
Palmer does not disclose, but Wakchaure discloses
set each plane of the plurality of planes to a ready status or a busy status (eg., 0065 Fig. 9B - FIG. 9B illustrates independent ready signals for each plane: RDY_P0 for plane 0, RDY_P1 for plane 1, RDY_P2 for plane 2, and RDY_P3 for plane 3).
a control logic circuit configured to control the plurality of planes based on the commands, and, among the commands (eg., 0017 - Separate command state machines for each plane on the memory-side enable the memory to accept and process commands independently for each plane);
determine a target plane (eg., 0041 - the commands will be forwarded to the plane queues 502-0-502-3 based on the target plane indicated in the command)
wherein the input/output controller is configured to change the target plane from the ready status to the busy status when a read operation time is started in response to the fixed-time read command in the target plane, and restore the target plane from the busy status to the ready status after the delay time has elapsed based on the read operation time having ended (eg., 0065 Fig. 9B - independent state machines on the NAND die for each plane's status cause the appropriate logic values to be driven on the independent ready signals. The independent ready signals enable each planes' status to be independently updated and tracked, which enables plane-level operations to have independent start and completion times. FIG. 9B shows that a read command to address A0 targeting plane 0 is received first, which causes the RDY_P0 signal to transition to a logic 0 at time t0 to indicate plane 0 is busy. A second read command on plane 1 is received and started while plane 0 is busy. In response to starting the plane 1 command, the RDY_P1 signal transitions to a logic 0 at time t1 to indicate that plane 1 is busy. A third read command on plane 2 is received and started while both plane 0 and plane 1 are busy. In response to starting the plane 2 command, the RDY_P2 signal transitions to a logic 0 at time t2 to indicate that plane 2 is busy. At time t3, the first command on plane 0 completes, causing the RDY_P0 signal to transition to a logic 1.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, providing the benefit of independent plane-level commands enable significant performance increases by enabling commands to start independently on each plane. In one such example, separate plane-level queues on the controller-side enable commands to be queued and dispatched independently to the planes. Separate ready/busy signals for each plane enable the controller to poll the memory at a plane-level to track completion and readiness of each plane for receiving additional commands. Thus, commands can be serviced independently per plane, enabling performance metrics such as performance/density (see Wakchaure, 0017).
Palmer in view of Wakchaure does not disclose, but Ishii discloses
a bit level; the bit level (eg., 0131 Fig. 9 - The command “01h/02h/03h” is a command for instructing an operation in the TLC method, and when any one of the commands is selected, a bit level to be read may be designated… read operation in TLC; 0042] The timer 26 is used in various operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Ishii providing the benefit of a semiconductor storage device capable of improving the reliability of a read operation (see Ishii, 0028) the NAND interface circuit 27 transmits/receives input/output signals I/O to/from the semiconductor storage device 10, transmits various control signals based on the commands received from the CPU 23 to the semiconductor storage device 10, and receives a ready/busy signal RBn from the semiconductor storage device 10 (0043).
Claim 2. Palmer in view of Wakchaure does not disclose, but Ishii discloses
wherein the read operation time varies according to the bit level, and a delay time according to the bit level is determined as a time at which busy status periods according to the bit level are same (eg., 0186 - the timer 26 counts the elapsed time from the completion of the dummy read period. Then, the memory system 1 proceeds to a normal operation state in which operations are made in response to instructions from the host device 30 (step S21). In the normal operation, for example, the CPU 23 monitors the count of the timer 26.; 0131 Fig. 9 - The command “01h/02h/03h” is a command for instructing an operation in the TLC method, and when any one of the commands is selected, a bit level to be read may be designated… read operation in TLC; 0042] The timer 26 is used in various operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Ishii providing the benefit of a semiconductor storage device capable of improving the reliability of a read operation (see Ishii, 0028) the NAND interface circuit 27 transmits/receives input/output signals I/O to/from the semiconductor storage device 10, transmits various control signals based on the commands received from the CPU 23 to the semiconductor storage device 10, and receives a ready/busy signal RBn from the semiconductor storage device 10 (0043).
Claim 4. Palmer in view of Wakchaure does not disclose, but Ishii discloses
wherein the read operation time varies according to the bit level, and a delay time according to the bit level is determined so that a difference between busy status periods according to the bit level is within a time required for receiving the commands (eg., 0186 - the timer 26 counts the elapsed time from the completion of the dummy read period. Then, the memory system 1 proceeds to a normal operation state in which operations are made in response to instructions from the host device 30 (step S21). In the normal operation, for example, the CPU 23 monitors the count of the timer 26.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Ishii providing the benefit of a semiconductor storage device capable of improving the reliability of a read operation (see Ishii, 0028) the NAND interface circuit 27 transmits/receives input/output signals I/O to/from the semiconductor storage device 10, transmits various control signals based on the commands received from the CPU 23 to the semiconductor storage device 10, and receives a ready/busy signal RBn from the semiconductor storage device 10 (0043).
Claim 5. Palmer discloses wherein the status delay logic is configured to store a delay time based on the bit level (eg., [0064] The delay time period can be implemented by a timer that can be a software or hardware-based timer. For example, upon receiving the first read request at 504 or 512 the controller can set a timer with a time out value of X.).
Claim 6. Palmer does not disclose, but Wakchaure discloses
wherein the input/output controller is configured to control status signals indicating the ready status or the busy status of each plane of the plurality of planes (eg., 0065 Fig. 9B - FIG. 9B illustrates independent ready signals for each plane: RDY_P0 for plane 0, RDY_P1 for plane 1, RDY_P2 for plane 2, and RDY_P3 for plane 3).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, providing the benefit of independent plane-level commands enable significant performance increases by enabling commands to start independently on each plane. In one such example, separate plane-level queues on the controller-side enable commands to be queued and dispatched independently to the planes. Separate ready/busy signals for each plane enable the controller to poll the memory at a plane-level to track completion and readiness of each plane for receiving additional commands. Thus, commands can be serviced independently per plane, enabling performance metrics such as performance/density (see Wakchaure, 0017).
Claim 7. Palmer does not disclose, but Wakchaure discloses
wherein the input/output controller is configured to output a status flag indicating the ready status or the busy status of the target plane in response to a status read command for the target plane (eg., 0017 - Separate ready/busy signals for each plane enable the controller to poll the memory at a plane-level to track completion and readiness of each plane).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, providing the benefit of independent plane-level commands enable significant performance increases by enabling commands to start independently on each plane. In one such example, separate plane-level queues on the controller-side enable commands to be queued and dispatched independently to the planes. Separate ready/busy signals for each plane enable the controller to poll the memory at a plane-level to track completion and readiness of each plane for receiving additional commands. Thus, commands can be serviced independently per plane, enabling performance metrics such as performance/density (see Wakchaure, 0017).
Claim 8. Palmer discloses wherein each plane of the plurality of planes is configured to perform a read operation in parallel in response to a plurality of fixed-time read commands sequentially received from the input/output controller (eg., 0061 - the NAND can be designed to allow for parallel execution of read commands for a particular portion of a NAND die. To maximize the probability that multiple read commands are executed in parallel, an intentional delay can be introduced into the read command processing.).
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Wakchaure (US 20190227749) and Ishii (US 20180246660) and further in view of Lin (US 20250224871)
Claim 9. Palmer in view of Wakchaure and Ishii does not disclose, but Lin discloses
wherein the input/output controller is configured to sequentially output data read from each plane of the plurality of planes in response to data output commands received through the channel (eg., 0076 - At 640, in some examples, the memory device 130 may output the first read command based on identifying the ready status of the first plane and may output a single-plane read command of the set of multiple of single-plane read commands for the respective plane based on the identifying the ready status of the respective plane. In some examples, the memory device 130 may further obtain first data associated with the first plane based on initiating the transfer for the first plane. In some examples, initiating the transfer for the respective plane and identifying the ready status of the respective plane may be concurrent with obtaining the first data (e.g., may occur during a same duration).).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Ishii with Lin, providing the benefit of enable a memory system 110 to support enhanced processing of multi-plane read commands (e.g., including separating a multi-plane read commands into one or more single-plane read commands) (see Lin, 0069).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Wakchaure (US 20190227749) and Ishii (US 20180246660) and further in view of Kim (US 20150049547)
Claim 10. Palmer in view of Wakchaure, Ishii does not disclose, but Kim discloses
wherein the multi-level cells are Triple Level Cells (TLC), and the status delay logic is configured to determine the delay time to different times based on whether the bit level is a Most Significant Bit (MSB), a Central Significant Bit (CSB), or a Least Significant Bit (LSB) based on the received address (eg., 0108, Fig. 13 - FIG. 13, the data read time associated with the read latency may further include delay times such as signal transfers between the memory controller and the memory device; 0117 - FIG. 19 illustrates an example of the 2-bit soft decision read operation and an example of the 3-bit soft decision read operation performed when first bits (e.g., LSBs) of data are read from the 3-bit MLCs by using a first reference read voltage VREF1. FIG. 20 illustrates an example of the 2-bit soft decision read operation and an example of the 3-bit soft decision read operation performed when second bits (e.g., CSBs) of data are read from the 3-bit MLCs by using second and third reference read voltages VREF2 and VREF3, and FIG. 21 illustrates an example of the 2-bit soft decision read operation and an example of the 3-bit soft decision read operation performed when third bits (e.g., MSBs) of data are read from the 3-bit MLCs by using fourth through seventh reference read voltages VREF4, VREF5, VREF6 and VREF7.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Ishii with Kim, providing the benefit of controlling a read sequence of a nonvolatile memory device (see Kim, 0002) adaptively define an appropriate read sequence in accordance with change(s) in memory system operating conditions (0007).
Claims 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Wakchaure (US 20190227749) and further in view of Kim (US 20150049547)
Claim 13. Palmer discloses A nonvolatile memory (eg., 0038 – Fig. 2 - 3D NAND architecture semiconductor memory array 200), comprising:
a plurality of planes (eg., 0040 - NAND memory device can include, 548 blocks per plane, and 4 or more planes per device),
each plane of the plurality of planes including a plurality of word lines (eg., 0041 - word lines (WL) WL0.sub.0-WL7.sub.0 210A-217A, WL0.sub.1-WL7.sub.1 210B-217B, etc.),
a plurality of bit lines (eg., 0039 - bit lines (BL) BL0-BL2 220-222)), and
a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines, wherein the plurality of memory cells are multi-level cells (eg., 0038 Fig. 2 - strings of memory cells (e.g., first-third A.sub.0 memory strings 205A.sub.0-207A.sub.0, );
detect a plurality of fixed-time read commands for the plurality of planes; a status delay logic configured to and based on an address received with the fixed-time read command, and determine a delay time based on (eg., 0062 Fig. 5 - Multiplane read compatible read commands are two read commands targeting two different portions of a same memory (e.g., NAND) die. Rather than immediately issue the first read request, the memory controller delays issuing the read command to the memory array until the earliest of the expiry of the delay time period or the receipt of a multiplane read compatible read command (e.g., a second read request to a second portion of the first die))
an input/output controller configured to change the plurality of planes (eg., 0057 Fig. 4 - input/output (I/O) circuit 426 can transfer values of data in or out of the memory device 400).
Palmer does not disclose, but Wakchaure discloses
set each plane of the plurality of planes to a ready status or a busy status (eg., 0065 Fig. 9B - FIG. 9B illustrates independent ready signals for each plane: RDY_P0 for plane 0, RDY_P1 for plane 1, RDY_P2 for plane 2, and RDY_P3 for plane 3).
a control logic circuit configured to control the plurality of planes based on the commands, (eg., 0017 - Separate command state machines for each plane on the memory-side enable the memory to accept and process commands independently for each plane);
wherein the input/output controller is configured to change the plurality of planes from the ready status to a busy status in an order in which the plurality of fixed-time read commands are received, and restore the busy status to the ready status after respective delay times have elapsed based on respective read operation times of the plurality of fixed-time read commands having ended (eg., 0065 Fig. 9B - independent state machines on the NAND die for each plane's status cause the appropriate logic values to be driven on the independent ready signals. The independent ready signals enable each planes' status to be independently updated and tracked, which enables plane-level operations to have independent start and completion times. FIG. 9B shows that a read command to address A0 targeting plane 0 is received first, which causes the RDY_P0 signal to transition to a logic 0 at time t0 to indicate plane 0 is busy. A second read command on plane 1 is received and started while plane 0 is busy. In response to starting the plane 1 command, the RDY_P1 signal transitions to a logic 0 at time t1 to indicate that plane 1 is busy. A third read command on plane 2 is received and started while both plane 0 and plane 1 are busy. In response to starting the plane 2 command, the RDY_P2 signal transitions to a logic 0 at time t2 to indicate that plane 2 is busy. At time t3, the first command on plane 0 completes, causing the RDY_P0 signal to transition to a logic 1.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, providing the benefit of independent plane-level commands enable significant performance increases by enabling commands to start independently on each plane. In one such example, separate plane-level queues on the controller-side enable commands to be queued and dispatched independently to the planes. Separate ready/busy signals for each plane enable the controller to poll the memory at a plane-level to track completion and readiness of each plane for receiving additional commands. Thus, commands can be serviced independently per plane, enabling performance metrics such as performance/density (see Wakchaure, 0017).
Palmer in view of Wakchaure does not disclose, but Kim discloses
wherein an order in which the plurality of fixed-time lead commands are received and an order in which the plurality of planes are restored from the busy status to the ready status are consistent with each other (eg., 0163 - the memory controller 2320 is configured to store a plurality of read sequences that are set to respectively correspond to operating conditions different from each other, perform the read sequences selectively based on sequence selection rates respectively corresponding to the read sequences, monitor read latencies of the respective read sequences and adjust the sequence selection rates based on monitoring results of the read latencies).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Ishii with Kim, providing the benefit of controlling a read sequence of a nonvolatile memory device (see Kim, 0002) adaptively define an appropriate read sequence in accordance with change(s) in memory system operating conditions (0007).
Claim 14. Palmer discloses of wherein the plurality of planes are configured to perform read operations in parallel in response to the plurality of fixed-time read commands (eg., 0061 - the NAND can be designed to allow for parallel execution of read commands for a particular portion of a NAND die. To maximize the probability that multiple read commands are executed in parallel, an intentional delay can be introduced into the read command processing.).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Wakchaure (US 20190227749) and further in view of Kim (US 20150049547) and further in view of Lin (US 20250224871)
Claim 15. Palmer in view of Wakchaure and Kim does not disclose, but Lin discloses
wherein the input/output controller is configured to sequentially output data items read from the plurality of planes in an order in which the plurality of planes are restored from the busy status to the ready statuschannel (eg., 0076 - At 640, in some examples, the memory device 130 may output the first read command based on identifying the ready status of the first plane and may output a single-plane read command of the set of multiple of single-plane read commands for the respective plane based on the identifying the ready status of the respective plane. In some examples, the memory device 130 may further obtain first data associated with the first plane based on initiating the transfer for the first plane. In some examples, initiating the transfer for the respective plane and identifying the ready status of the respective plane may be concurrent with obtaining the first data (e.g., may occur during a same duration).).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure, with Kim with Lin, providing the benefit of enable a memory system 110 to support enhanced processing of multi-plane read commands (e.g., including separating a multi-plane read commands into one or more single-plane read commands) (see Lin, 0069).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Wakchaure (US 20190227749) and further in view of Kim (US 20150049547) and further in view of Ishii (US 20180246660)
Claim 16. Palmer in view of Wakchaure and Kim does not disclose, but Ishii discloses
wherein a delay time of each of the plurality of planes is determined based on a bit level of target subpages indicated by addresses received together with the plurality of fixed- time read commands (eg., 0131 Fig. 9 - The command “01h/02h/03h” is a command for instructing an operation in the TLC method, and when any one of the commands is selected, a bit level to be read may be designated… read operation in TLC; 0042] The timer 26 is used in various operations).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer with Wakchaure and Kim, with Ishii providing the benefit of a semiconductor storage device capable of improving the reliability of a read operation (see Ishii, 0028) the NAND interface circuit 27 transmits/receives input/output signals I/O to/from the semiconductor storage device 10, transmits various control signals based on the commands received from the CPU 23 to the semiconductor storage device 10, and receives a ready/busy signal RBn from the semiconductor storage device 10 (0043).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Kim (US 20150049547)
Claim 17. Palmer discloses A storage device (eg., 0038 – Fig. 2 - 3D NAND architecture semiconductor memory array 200),
a plurality of nonvolatile memories, each nonvolatile memory of the plurality of nonvolatile memories including a plurality of planes (eg., 0026 - a number of individual memory die (e.g., a stack of three-dimensional (3D) NAND die, one or more NAND dies, or the like); 0021 - multiplane read );
a storage controller configured to control the plurality of nonvolatile memories (eg., 0028 - he memory controller 115 can include one or more memory control units, circuits, or components configured to control access across the memory array 120 ); and
a plurality of channels configured to connect the storage controller and the plurality of nonvolatile memories (eg., 0051 - the channels, between the sources and drains) of the memory cells),
wherein the storage controller is configured to receive a plurality of read requests from a host (eg., [0069] Read component 746 can handle read requests by hosts),
schedule fixed-time read commands for the plurality of nonvolatile memories based on target latencies of the plurality of read requests (eg., 0022 - length of the delay period can be dynamic and can adjust based upon the host workload to maximize the benefits of multiplane read and minimize the penalty to overall command latency and throughput. While the disclosed methods increase read command latency of a single command by a small amount, the overall system latency can be reduced by executing more read commands in parallel.), and
interleave the for the plurality of planes included in the plurality of nonvolatile memories based on a scheduled order, and wherein each of the plurality of nonvolatile memories is configured to perform fixed-time read operations in parallel on the plurality of planes in response to the fixed-time read commands (eg., 0065 - a delay period timer can be started at operation 604 and the request queued at operation 606. If the queue is not empty and a compatible multiplane read request is pending, then at operation 608, both the request received at operation 602 and the queued request can be issued as a multiplane read command for execution in parallel.), and
fixed-time read commands (eg., 0062 Fig. 5 - Multiplane read compatible read commands are two read commands targeting two different portions of a same memory (e.g., NAND) die. Rather than immediately issue the first read request, the memory controller delays issuing the read command to the memory array until the earliest of the expiry of the delay time period or the receipt of a multiplane read compatible read command (e.g., a second read request to a second portion of the first die)) .
Palmer does not disclose, but Kim discloses
provide responses for the to the storage controller in a same order as an order in which the fixed-time read commands are received (eg., 0163 - the memory controller 2320 is configured to store a plurality of read sequences that are set to respectively correspond to operating conditions different from each other, perform the read sequences selectively based on sequence selection rates respectively corresponding to the read sequences, monitor read latencies of the respective read sequences and adjust the sequence selection rates based on monitoring results of the read latencies).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer, with Ishii with Kim, providing the benefit of controlling a read sequence of a nonvolatile memory device (see Kim, 0002) adaptively define an appropriate read sequence in accordance with change(s) in memory system operating conditions (0007).
Claim 18. Palmer discloses of wherein the storage controller is configured to provide fixed-time read commands for nonvolatile memories connected to one channel of the plurality of channels, to the one channel according to the scheduled order (eg., 0065 Fig. 6 - a delay period timer can be started at operation 604 and the request queued at operation 606. If the queue is not empty and a compatible multiplane read request is pending, then at operation 608, both the request received at operation 602 and the queued request can be issued as a multiplane read command for execution in parallel).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Kim (US 20150049547) and further in view of Wakchaure (US 20190227749)
Claim 19. Palmer in view of Kim does not disclose, but Wakchaure discloses
wherein the storage controller is configured to: provide a status read command for each plane of the plurality of planes to each nonvolatile memory of the plurality of nonvolatile memories (eg., 0058 - the “Status by plane” command enables the controller to poll the status of individual planes.), and
provide data output commands to each nonvolatile memory of the plurality of nonvolatile memories for the plurality of planes in an order in which ready statuses of the plurality of planes are detected (eg., [0059] The enhanced Read column commands enable the data output for the desired Column/Plane/LUN address specified in the sequence. Thus, in one example, the enhanced read column enhanced command by plane is issued by the controller after a read command to check status and clock out the data. The sequence includes a read status by plane command (72h) followed by 03h and E0h commands to clock out the data. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer and Kim with Wakchaure, providing the benefit of independent plane-level commands enable significant performance increases by enabling commands to start independently on each plane. In one such example, separate plane-level queues on the controller-side enable commands to be queued and dispatched independently to the planes. Separate ready/busy signals for each plane enable the controller to poll the memory at a plane-level to track completion and readiness of each plane for receiving additional commands. Thus, commands can be serviced independently per plane, enabling performance metrics such as performance/density (see Wakchaure, 0017).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US 20200135278) and in view of Kim (US 20150049547) and further in view of Park (US 20190227719)
Claim 20. Palmer in view of Kim does not disclose, but Park discloses
wherein the storage controller is configured to provide responses for the plurality of read requests to the host based on the responses received from the plurality of nonvolatile memories (eg., 0153 - [0153] During a read operation, the processor 1010 may derandomize data received from the memory device 100. For example, the processor 1010 may use a derandomizing seed to derandomize data received from the memory device 100. Derandomized data may be output to the host.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the semiconductor memory with bit lines and word lines and memory cells on planes as disclosed by Palmer, with Ishii with Park, providing the benefit of NAND memory devices can be designed such that multiple reads to different portions of a single die can be done in parallel. This may be called multiplane read. As use herein portions of the die refer generically to different planes, or different plane groups (e.g., a group of two or more planes can constitute a plane group) of a same die which may execute read commands simultaneously (see Palmer, 0021).
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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