DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 1 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims of prior U.S. Patent No. 11,984,888. This is a statutory double patenting rejection.
Application: 19/285,497
Claim 1:
An apparatus, comprising: an inverter having an input terminal and an output terminal; a first N-channel field effect transistor (NFET) and a first P channel field effect transistor (PFET) with their drain terminals shorted together at the output terminal of the inverter, a source terminal of the first NFET and a source terminal of the first PFET are connected to a ground and a power supply, respectively; a second PFET having a source terminal and a drain terminal configured to couple the output terminal of the inverter to a harvest terminal whose capacitance holds harvested charge at a voltage lower than a voltage of the power supply; the input terminal and the output terminal of the inverter, during operation, having electric potentials making full-swing transitions between the voltage of the power supply and a voltage of the ground, the input terminal of the inverter connected directly to a gate input terminal of the first PFET; a second NFET having a gate input terminal configured to be driven by the input terminal of the inverter and having a source terminal and a drain terminal connected to the ground and the output terminal of the inverter, respectively; and a 2-input gate with its inputs configured to be driven by the input terminal and the output terminal of the inverter, the 2-input gate having an output terminal configured to drive a gate input terminal of the second PFET and an input terminal of a delay element having an inverted output configured to drive the first NFET of the inverter.
USP 11,984,888
Claim 1:
An apparatus, comprising: an inverter having an input terminal and an output terminal; a first N-channel field effect transistor (NFET) and a first P channel field effect transistor (PFET) with their drain terminals shorted together at the output terminal of the inverter, a source terminal of the first NFET and a source terminal of the first PFET are connected to a ground and a power supply, respectively; a second PFET having a source terminal and a drain terminal configured to couple the output terminal of the inverter to a harvest terminal whose capacitance holds harvested charge at a voltage lower than a voltage of the power supply; the input terminal and the output terminal of the inverter, during operation, having electric potentials making full-swing transitions between the voltage of the power supply and a voltage of the ground, the input terminal of the inverter connected directly to a gate input terminal of the first PFET; a second NFET having a gate input terminal configured to be driven by the input terminal of the inverter and having a source terminal and a drain terminal connected to the ground and the output terminal of the inverter, respectively; and a 2-input NAND gate with its inputs configured to be driven by the input terminal and the output terminal of the inverter, the 2-input NAND gate having an output terminal configured to drive a gate input terminal of the second PFET and an input terminal of a delay element having an inverted output configured to drive the first NFET of the inverter.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2836 8/14/2026
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