DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 19/285,608 filed on 7/30/2025 which is a continuation of application 18/508,112 filed on 11/13/2026 which claims priority to provisional application 63/385,011 filed on 11/26/2022.
Claims 1-20 have been examined.
Claim Interpretation
Claims 7-8 are method claims that include one or more contingent clauses, such as “X in response to Y” and do not explicitly claim that the condition, Y, occurs. The broadest reasonable interpretation of these claims does not include those X steps. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04 (II).
Looking at claim 7, for example; the claim states, “determining an updated destination memory region of the plurality of memory regions, to store the user data for the zone in response to the invalidation time satisfying a threshold time.” but does not explicitly require the invalidation time to satisfy a threshold time. As a result, the broadest reasonable interpretation of the claims is that the determining an updated destination memory region of the plurality of memory regions, to store the user data for the zone step does not need to occur for the claim to be met by the prior art.
The examiner encourages the applicant to positively recite these conditions occurring in the claim limitations so that the resulting steps would occur under the broadest reasonable interpretation of each claim.
Claim 8 presents limitations that further limit the resulting steps of the contingent limitation and as such also are not required limitations under the broadest reasonable interpretation of the claims.
For the purpose of compact prosecution, the examiner is treating these claims/limitations as if they were positively recited so that they can be evaluated in view of the prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 7-10, 15-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno (US 2021/0064287), Mao et al. (US 2022/0365875), and Li (US 2018/0121109).
With respect to claim 1, Kanno teaches of a method comprising: receiving, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device, wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid (fig. 3, 19; paragraph 90, 221-222; where a write command is received from the host that indicates the lifetime of the data included in the write command);
determining a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint, wherein data stored in the destination memory region is segregated by the corresponding zone (fig. 3, 19; paragraph 90-93, 223; where the controller identifies the period to which the estimated lifetime or write data belongs. Each period corresponds to a set of blocks/block group that has been allocated to store data with a particular lifetime); and
writing the user data for the zone to the destination memory region (fig. 3, 19; paragraph 91-93, 223; where the data is written to a block in the group allocated to store data with the same lifetime).
Kanno fails to explicitly teach of (1) each of the plurality of zones is written sequentially, and rewriting or modifying any data within the zone results in resetting the zone (2) determining that the zone has been fully written to a source memory region, wherein data stored in the source memory region is not segregated by a corresponding zone and (3) moving the user data for the zone from the source memory region to the destination memory region.
However, Mao teaches of receiving, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device, wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid, each of the plurality of zones is written sequentially, and rewriting or modifying any data within the zone results in resetting the zone (fig. 7; paragraphs 200, 286-289; where each zone of a zoned namespace is a logical block address range that must be written sequentially and explicitly reset before rewriting. The computing device indicates in metadata provided with the data a property such as the longevity of the data blocks. For example: short term, longer term, or some other appropriate period of time).
The combination of Kanno and Mao fails to explicitly teach of (1) determining that the zone has been fully written to a source memory region, wherein data stored in the source memory region is not segregated by a corresponding zone and (2) moving the user data for the zone from the source memory region to the destination memory region.
However, Li teaches of determining that the zone has been fully written to a source memory region, wherein data stored in the source memory region is not segregated by a corresponding zone (paragraph 23, 34; where a write-back cache using MRAM is implemented in the controller and once the data is held in the write-back cache the SSD acknowledges the host. The write-back cache is not divided into lifetime groups/zones).
The combination of Kanno and Li teaches of moving the user data for the zone from the source memory region to the destination memory region (Kanno, fig. 3, 19; paragraph 91-93, 223; Li, paragraph 23, 34; where in the combination the data is written back to the flash memory into a block in the group allocated to store data with the same lifetime).
Kanno and Mao are analogous art because they are from the same field of endeavor, as they are directed to data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of Kanno and Mao before the time of the effective filing of the claimed invention to incorporate using the zoned namespace storage of Mao in Kanno. Their motivation would have been to more efficiently place data (Mao, paragraph 200).
Kanno, Mao, and Li are analogous art because they are from the same field of endeavor, as they are directed to data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of Kanno, Mao, and Li before the time of the effective filing of the claimed invention to incorporate a write-back cache using MRAM into the controller of the combination of Kanno and Mao as taught by Li. Their motivation would have been to reduce power consumption and cost of the storage (Li, abstract).
With respect to claim 9, Kanno, Mao, and Li teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Kanno also teaches of a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to carry out the method of claim 1 (paragraph 88; where the firmware is loaded from ROM to carry out the controller’s operations).
With respect to claims 2 and 10, the combination of Kanno, Mao, and Li teaches of wherein the source memory region is a first type of non-volatile memory element (Li, paragraph 23, 34; where the write-back cache is MRAM), and
the plurality of memory regions comprise a first destination memory region, which is a second type of non-volatile memory element and a second destination memory region, which is a third type of non-volatile memory element (Kanno, fig. 4; paragraph 36, 39, 77-79, 237; where NAND flash memory includes a plurality of NAND flash dies that are independently operable. Each NAND flash memory device can either be of a first or second type. The NAND flash memory can also comprise MRAM, PRAM, ReRAM, or FeRAM).
The reasons for obviousness are the same as indicated above with respect to claim 1.
With respect to claim 17, Kanno, Mao, and Li teaches of the limitations cited and described above with respect to claims 1-2 for the same reasoning as recited with respect to claims 1-2.
Kanno also teaches of a system comprising: a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to carry out the method of claim 1 (fig. 3; paragraphs 76, 85; where the flash storage device includes a controller including a CPU and NAND flash memory).
With respect to claims 7, 15, and 20 Kanno teaches of determining an invalidation time for the user data, wherein the invalidation time is a time since data in the user data has been invalidated (fig. 20; paragraph 90, 227-233; where the end of the lifetime for the data has elapsed which signifies the data is no longer valid);
determining an updated destination memory region of the plurality of memory regions, to store the user data for the zone in response to the invalidation time satisfying a threshold time (fig. 20; paragraph 90, 227-233; as the lifetime period for the data has elapsed, which signifies the data is no longer valid, it is determined if a new lifetime is reestimated for the data and the data that is valid (has not been modified or erased) is moved to the block group that corresponds to the reestimated lifetime); and
moving the user data for the zone from the destination memory region to the updated destination memory region (fig. 20; paragraph 90, 227-233; anew lifetime is reestimated for the data and the data that is valid (has not been modified or erased) is moved to the block group that corresponds to the reestimated lifetime).
With respect to claims 8 and 16, Kanno teaches of wherein determining the updated destination memory region is further based on the lifetime hint (fig. 20; paragraph 90, 227-233; where the reestimated lifetime identifies the block group where the data is copied).
Claim(s) 3, 5-6, 11, 13-14, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno, Mao, and Li as applied to claims 2, 10, and 17 above, and further in view of Cheng (US 2013/0326121).
With respect to claims 3, 11, and 18, the combination of Kanno, Mao, and Li teaches of wherein the source memory region comprises a first logical to physical data structure (Kanno, fig. 3, paragraph 116; where the DRAM (in the combination the MRAM) stores an address translation table),
The combination of Kanno, Mao, and Li fails to explicitly teach of the first destination memory region comprises a second logical to physical data structure and a first zone mapping data structure, and the second destination memory region comprises a second zone mapping data structure.
However, Cheng teaches of the first destination memory region comprises a second logical to physical data structure and a first zone mapping data structure, and the second destination memory region comprises a second zone mapping data structure (fig. 1, paragraph 27-29, 44-45; where the flash memory stores an invalid block record that shows for each block whether or not it is invalid and also stores the logical to physical address mapping tables which are organized by group such that each group has its own logical to physical mapping table showing which physical locations are in each group).
Kanno, Mao, Li, and Cheng are analogous art because they are from the same field of endeavor, as they are directed to data storage.
It would have been obvious to one of ordinary skill in the art having the teachings Kanno, Mao, Li, and Cheng before the time of the effective filing of the claimed invention to incorporate backing up the management tables into the flash memory in the combination of Kanno, Mao, and Li as taught in Cheng. Their motivation would have been to retain the data in case of a power loss.
With respect to claim 5 and 13, Cheng teaches of wherein the second logical to physical data structure tracks invalidated data in the first destination memory region and the first zone mapping data structure tracks where zones of the plurality of zones are stored in the first destination memory region (fig. 1, paragraph 27-29, 44-45; where the flash memory stores an invalid block record that shows for each block whether or not it is invalid and also stores the logical to physical address mapping tables which are organized by group such that each group has its own logical to physical mapping table showing which physical locations are in each group).
The reasons for obviousness are the same as indicated above with respect to claim 3.
With respect to claims 6 and 14, Cheng teaches of wherein the second zone mapping data structure tracks where zones of the plurality of zones are stored in the second destination memory region (fig. 1, paragraph 27-29, 44-45; where the flash memory stores the logical to physical address mapping tables which are organized by group such that each group has its own logical to physical mapping table showing which physical locations are in each group).
The reasons for obviousness are the same as indicated above with respect to claim 3.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,393,361 in view of Mao.
While the claimed limitations of US 12,393,361 do not include all the limitations of the present claims. The present claims are obvious over the claims of US 12,393,361 in view of Mao.
US 12,393,361 fails to explicitly claim, each of the plurality of zones is written sequentially, and rewriting or modifying any data within the zone results in resetting the zone. However, Mao teaches this in paragraph 200, where each zone of a zoned namespace is a logical block address range that must be written sequentially and explicitly reset before rewriting.
The claims of US 12,393,361 and Mao are analogous art because they are from the same field of endeavor, as they are directed to data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of the claims of US 12,393,361 and Mao before the time of the effective filing of the claimed invention to incorporate using the zoned namespace storage of Mao in the claims of US 12,393,361. Their motivation would have been to more efficiently place data (Mao, paragraph 200).
See the chart below for a mapping of the rejected claims.
Application 19/285,608
US 12,393,361
Claim 1: A method comprising: receiving, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device,
Claim 1: A method comprising: receiving, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device,
wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid,
wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid;
each of the plurality of zones is written sequentially, and rewriting or modifying any data within the zone results in resetting the zone;
determining that the zone has been fully written to a source memory region, wherein data stored in the source memory region is not segregated by a corresponding zone;
determining that the zone has been fully written to a source memory region, wherein data stored in the source memory region is not segregated by a corresponding zone and wherein the source memory region comprises a first logical to physical data structure that tracks a corresponding zone of the plurality of zones for data in the source memory region;
determining a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint,
determining a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint,
wherein data stored in the destination memory region is segregated by the corresponding zone; and
wherein data stored in the destination memory region is segregated by the corresponding zone; and
moving the user data for the zone from the source memory region to the destination memory region.
moving the user data for the zone from the source memory region to the destination memory region.
Claim 2
Claim 2
Claim 3
Claim 1, 3
Claim 4
Claim 1
Claim 5
Claim 4
Claim 6
Claim 5
Claim 7
Claim 6
Claim 8
Claim 7
Claim 9: A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
Claim 8: A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device,
receive, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device,
wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid,
wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid;
each of the plurality of zones is written sequentially, and rewriting or modifying any data within the zone results in resetting the zone;
determine that the zone has been fully written to a source memory region;
determine that the zone has been fully written to a source memory region, wherein data stored in the source memory region is not segregated by a corresponding zone and wherein the source memory region comprises a first logical to physical data structure that tracks a corresponding zone of the plurality of zones for data in the source memory region;
determine a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint; and
determine a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint, wherein data stored in the destination memory region is segregated by the corresponding zone; and
move the user data for the zone from the source memory region to the destination memory region.
move the user data for the zone from the source memory region to the destination memory region.
Claim 10
Claim 9
Claim 11
Claim 8, 10
Claim 12
Claim 8
Claim 13
Claim 11
Claim 14
Claim 12
Claim 15
Claim 13
Claim 16
Claim 14
Claim 17: A system comprising: a plurality of memory devices; and
Claim 15: A system comprising: a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to:
a processing device, operatively coupled with the plurality of memory devices, to:
receive, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device,
receive, from a host device, a lifetime hint for a zone of a plurality of zones in a memory device,
wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid,
wherein the lifetime hint is an estimation of a length of time user data for the zone will be valid;
each of the plurality of zones is written sequentially, and rewriting or modifying any data within the zone results in resetting the zone;
determine that the zone has been fully written to a source memory region, wherein the source memory region is a first type of non-volatile memory element;
determine that the zone has been fully written to a source memory region, wherein the source memory region is a first type of non-volatile memory element, wherein data stored in the source memory region is not segregated by a corresponding zone, and wherein the source memory region comprises a first logical to physical data structure that tracks a corresponding zone of the plurality of zones for data in the source memory region;
determine a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint, wherein the plurality of memory regions comprise a first destination memory region, which is a second type of non-volatile memory element and a second destination memory region, which is a third type of non-volatile memory element; and
determine a destination memory region, of a plurality of memory regions, to store the user data for the zone using the lifetime hint, wherein the plurality of memory regions comprise a first destination memory region, which is a second type of non-volatile memory element and a second destination memory region, which is a third type of non-volatile memory element; and
move the user data for the zone from the source memory region to the destination memory region.
move the user data for the zone from the source memory region to the destination memory region.
Claim 18
Claim 15, 16
Claim 19
Claim 15, 17
Claim 20
Claim 18
Allowable Subject Matter
Claims 4, 12, and 19 would be allowable if rewritten to overcome the double patenting rejection(s), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 4, 12, and 19, the prior art does not teach or suggest, “wherein the first logical to physical data structure tracks a corresponding zone of the plurality of zones for data in the source memory region,” in the context of each the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jeon (US 2022/0113885) discloses maintaining a preset lifetime (P/E cycles) for storing multi-bit data in the memory cells. The preset lifetime is used to adjust the memory block to store one-bit data in the memory cells which can lengthen the lifespan of the memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
