Prosecution Insights
Last updated: October 27, 2026
Application No. 19/286,154

MEDIA SCAN METHOD TO REDUCE ACTIVE IDLE POWER OF MEMORY DEVICES

Non-Final OA §DOUBLEPATENT
Filed
Jul 30, 2025
Priority
Mar 02, 2023 — provisional 63/449,465 +1 more
Examiner
PAPERNO, NICHOLAS A
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
208 granted / 290 resolved
+11.7% vs TC avg
Minimal -3% lift
Without
With
+-3.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
13 currently pending
Career history
306
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
10.4%
-29.6% vs TC avg
§112
14.0%
-26.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 290 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4-9, 13-16, and 17-20 of U.S. Patent No. 12,504,896. Although the claims at issue are not identical, they are not patentably distinct from each other because the independent claims of the instant application are identical to the dependent claims of the patent and would overlap in scope regarding those claims. Instant Application Patent 12,504,896 1. A method comprising: performing, by a processing device of a memory sub-system controller, a media scan operation on one more memory devices coupled to the memory sub-system controller while at least one other processing device of the memory sub-system controller is in a sleep mode; determining, by the processing device, a number of media scan operations to be performed in a predetermined period of time; and performing, by the processing device, a burst scan operation comprising two or more of the media scan operations to be performed in the predetermined period of time to increase a time period between the burst scan operation and a subsequent burst scan operation. 4. The method of claim 1, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices. 5. The method of claim 1, further comprising: combining the two or more of the media scan operations to be performed in the predetermined period of time. 4. The method of claim 1, further comprising: performing, by a third processing device of the memory sub-system controller, a media scan operation on the one more memory devices coupled to the memory sub-system controller while the first processing device and the second processing device are in the sleep mode. 7. The method of claim 4, wherein performing the media scan operation on one more memory devices further comprises: determining, by the third processing device, a number of media scan operations to be performed in a predetermined period of time, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and combining the media scan operations to be performed in the predetermined period of time and performing a burst scan operation comprising two or more of the media scan operations, thereby increasing a time period between the burst scan operation and a subsequent burst scan operation. 2. The method of claim 1, wherein the processing device comprises a back end processor, and wherein the at least one other processing device comprises at least one of an input/output read processor or a flash translation layer processor. 5. The method of claim 4, wherein the first processing device comprises an input/output read processor, the second processing device comprises a flash translation layer processor, and the third processing device comprises a back end processor. 3. The method of claim 1, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation. 6. The method of claim 4, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation. 6. The method of claim 1, further comprising: performing, simultaneously, the media scan operation on a plurality of channels coupling the one more memory devices to the memory sub-system controller. 8. The method of claim 4, wherein performing the media scan operation on one more memory devices further comprises: determining, by the third processing device, a number of media scan operations to be performed in a predetermined period of time, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and performing, simultaneously, the media scan operation on a plurality of channels coupling the one more memory devices to the memory sub-system controller. 7. The method of claim 1, further comprising: in response to determining that an input/output path of the memory sub-system controller is in sleep mode, transitioning, by the processing device, a volatile memory device coupled to the memory sub-system controller to a self-refresh mode. 9. The method of claim 4, further comprising: in response to determining that the input/output path is in sleep mode, transitioning, by the third processing device, a volatile memory device coupled to the memory sub-system controller to a self-refresh mode. 8. A system comprising: one or more memory devices; and a memory sub-system controller comprising a plurality of processing devices, operatively coupled to the one or more memory devices, to perform operations comprising: performing, by a first processing device of the memory sub-system controller, a media scan operation on the one more memory devices coupled to the memory sub- system controller while at least one other processing device of the memory sub-system controller is in a sleep mode; determining, by the first processing device, a number of media scan operations to be performed in a predetermined period of time; and performing, by the first processing device, a burst scan operation comprising two or more of the media scan operations to be performed in the predetermined period of time to increase a time period between the burst scan operation and a subsequent burst scan operation. 11. The system of claim 8, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices. 12. The system of claim 8, wherein the processing device is to perform operations further comprising: combining the two or more of the media scan operations to be performed in the predetermined period of time. 13. The system of claim 10, wherein the operations further comprise: performing a media scan operation on one more memory devices coupled to the memory sub-system controller while the first processing unit and the second processing unit are in the sleep mode. 15. The system of claim 13, wherein performing the media scan operation on one more memory devices further comprises: determining a number of media scan operations to be performed in a predetermined period of time, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and combining the media scan operations to be performed in the predetermined period of time and performing a burst scan operation comprising two or more of the media scan operations, thereby increasing a time period between the burst scan operation and a subsequent burst scan operation. 9. The system of claim 8, wherein the first processing device comprises a back end processor, and wherein the at least one other processing device comprises at least one of an input/output read processor or a flash translation layer processor. 14. The system of claim 13, wherein the first processing unit comprises an input/output read processor and the second processing unit comprises a flash translation layer processor. 10. The system of claim 8, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation. 6. The method of claim 4, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation. 13. The system of claim 8, wherein the processing device is to perform operations further comprising: performing, simultaneously, the media scan operation on a plurality of channels coupling the one more memory devices to the memory sub-system controller. 16. The system of claim 13, performing the media scan operation on one more memory devices further comprises: determining a number of media scan operations to be performed in a predetermined period of time, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and performing, simultaneously, the media scan operation on a plurality of channels coupling the one more memory devices to the memory sub-system controller. 14. The system of claim 8, wherein the processing device is to perform operations further comprising: in response to determining that an input/output path of the memory sub-system controller is in sleep mode, transitioning, by the processing device, a volatile memory device coupled to the memory sub-system controller to a self-refresh mode. 9. The method of claim 4, further comprising: in response to determining that the input/output path is in sleep mode, transitioning, by the third processing device, a volatile memory device coupled to the memory sub-system controller to a self-refresh mode. 15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device of a memory sub-system controller, cause the processing device to perform operations comprising: performing, by the processing device of the memory sub-system controller, a media scan operation on one more memory devices coupled to the memory sub-system controller while at least one other processing device of the memory sub-system controller is in a sleep mode; determining, by the processing device, a number of media scan operations to be performed in a predetermined period of time; and performing, by the processing device, a burst scan operation comprising two or more of the media scan operations to be performed in the predetermined period of time to increase a time period between the burst scan operation and a subsequent burst scan operation. 18. The non-transitory computer-readable storage medium of claim 15, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices. 19. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations further comprising: combining the two or more of the media scan operations to be performed in the predetermined period of time. 18. The non-transitory computer-readable storage medium of claim 17, wherein the operations further comprise: performing a media scan operation on one more memory devices coupled to the memory sub-system controller while the first processing unit and the second processing unit are in the sleep mode. 19. The non-transitory computer-readable storage medium of claim 18, wherein performing the media scan operation on one more memory devices further comprises: determining a number of media scan operations to be performed in a predetermined period of time, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and combining the media scan operations to be performed in the predetermined period of time and performing a burst scan operation comprising two or more of the media scan operations, thereby increasing a time period between the burst scan operation and a subsequent burst scan operation. 16. The non-transitory computer-readable storage medium of claim 15, wherein the processing device comprises a back end processor, and wherein the at least one other processing device comprises at least one of an input/output read processor or a flash translation layer processor. 5. The method of claim 4, wherein the first processing device comprises an input/output read processor, the second processing device comprises a flash translation layer processor, and the third processing device comprises a back end processor. 17. The non-transitory computer-readable storage medium of claim 15, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation. 6. The method of claim 4, wherein the media scan operation comprises one or more of a read operation, a write operation, or a sense operation. 20. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations further comprising: performing, simultaneously, the media scan operation on a plurality of channels coupling the one more memory devices to the memory sub-system controller. 20. The non-transitory computer-readable storage medium of claim 18, wherein performing the media scan operation on one more memory devices further comprises: determining a number of media scan operations to be performed in a predetermined period of time, wherein the number of media scan operations is based on a number of pages to be scanned in the one or more memory devices; and performing, simultaneously, the media scan operation on a plurality of channels coupling the one more memory devices to the memory sub-system controller. Allowable Subject Matter Claims 1-20 are allowed over the prior art. After careful consideration, examination, and search of the claimed invention, prior art was not found to teach the amended limitation to the independent claims “…performing…a media scan operation on one more memory devices coupled to the memory sub-system controller while at least one other processing device of the memory sub-system controller is in a sleep mode…and performing, by the processing device, a burst scan operation comprising two or more of the media scan operations to be performed in the predetermined period of time to increase a time period between the burst scan operation and a subsequent burst scan operation”. The following is an examiner' s statement of reasons for allowance: Derner et al. (US PGPub 2019/0279704, hereafter referred to as Derner) teaches putting a processor/device to sleep after a certain amount of time of inactivity has been detected. However, Derner does not teach the cited limitations to the independent claims. Chandrasekar et al. (US PGPub 2018/0102776, hereafter referred to as Chandrasekar) teaches IO channels with power saving (sleep) modes that can be put in a power saving mode when idle and taken out of that mode when needed. However, Chandrasekar does not teach the cited limitations to the independent claims. Robinson et al. (US PGPub 2015/0193027, hereafter referred to as Robinson) teaches a processor that can put itself and the components of the controller it is a part of to sleep when a certain period of inactivity is detected. However, Robinson does not teach the cited limitations to the independent claims. Fujii (Foreign Patent AU 2012200911) teaches multiple processors that can be in various states of powered on and sleep. However, Fujii does not teach the cited limitations to the independent claims. Neither alone nor in combination do the references teach the limitations of the independent claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS A PAPERNO whose telephone number is (571)272-8337. The examiner can normally be reached Mon-Fri 9:30-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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Prosecution Timeline

Jul 30, 2025
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
68%
With Interview (-3.2%)
2y 5m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 290 resolved cases by this examiner. Grant probability derived from career allowance rate.

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