CTNF 19/286,189 CTNF 90482 DETAILED ACTION This action is responsive to 07/30/2025. Claims 1-16 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-27 AIA Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/762,975 , filed on 3/23/2022 . Claim Objections 07-29-01 AIA Claim 3 objected to because of the following informalities: In line 1, insert “ wherein ” after “ claim 1, ” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 3, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US Patent 10,304,920), hereinafter Choi, in view of Cha et al. (US Patent 11,257,897), hereinafter Cha . Regarding claim 1 , Choi discloses a display panel ( an organic light emitting diode display device-see figs. 1-15 and [col. 2, ll. 39-41] ), comprising: a substrate ( substrate 110-fig. 7 ), an initialization signal line layer ( initialization voltage line 159-see fig. 7 ) and a first auxiliary signal line layer ( pixel conductive pattern 192 (192a, 192b, and 192c)-see figs. 7, 9-13, and 15 with description in [col. 13, ll. 38-52] ) sequentially stacked on the substrate along a direction away from the substrate( i.e., disposed on the passivation layer 180 away from substrate 110-see fig. 7 ) ; and a plurality of sub-pixel areas arranged in an array, wherein the plurality of sub-pixel areas form a plurality of rows of sub-pixel areas arranged in sequence along a second direction, each row of sub-pixel areas comprises a plurality of sub-pixel areas arranged along a first direction, the first direction and the second direction intersect ( i.e., a plurality of pixels that may display a predetermined color, for example, the plurality of pixels may include red (R), green (G), and blue (B) pixels disposed in a row direction (first direction) and arranged in a column direction (second direction)-see figs. 3 and 9 with description in [col. 7, ll. 38-47] ); wherein the initialization signal line layer comprises an initialization signal line pattern arranged in each of the plurality of sub-pixel areas ( initialization voltage line 159-see figs. 3 and 9 ); wherein the first auxiliary signal line layer comprises a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one- to-one manner( see, for example, fig. 15 and further description in [col. 13, ll. 38-50], wherein the pixel conductive pattern 192 (192a, 192b, and 192c) extends around pixel electrodes (191a, 191b, and 191c) for each row of pixels ) , and the first auxiliary signal line pattern is coupled to an initialization signal line pattern in a corresponding sub-pixel area ( see figs. with description in [col. 13, ll. 51-52], and [col. 16, ll. 37-42], wherein it is disclosed that the pixel conductive pattern 192 may transmit the initialization voltage Vint (col. 13, ll. 51-52) … passivation layer 180 includes a contact hole 88 (see fig. 9) disposed on the connector 175. The pixel conductive pattern 192 may transmit the initialization voltage Vint and may be electrically connected to the connector 175 through the contact hole 88 (co. 16, ll. 37-42]) ), at least part of the first auxiliary signal line pattern extends along the first direction ( straight part (192a, 192b, and 192c) extend to be mainly parallel to scan lines (151, 152, and 154)-see [col. 13, ll. 42-43]), i.e., extend along the first direction ), and first auxiliary signal line patterns corresponding to sub-pixel areas in a same row of sub-pixel areas are sequentially coupled ( the pixel conductive pattern 192 for each row of pixels is an integrated line-see figs. 3 and 9 ). Choi does not appear to expressly disclose and wherein there is a third overlapping area between an orthographic projection of the first auxiliary signal line pattern on the substrate and an orthographic projection of the initialization signal line pattern on the substrate, the first auxiliary signal line pattern is directly coupled to the initialization signal line pattern through a via hole located in the third overlapping area. Cha, in for example, fig. 9A with further description in [col. 21, ll. 53-65], illustrates a cross-sectional area of a display device taken along a line IX-IX’ of fig. 8A, wherein a portion of an auxiliary voltage line VL-R may be connected to a first initialization voltage line VL-A through a first contact hole CNT1, similarly, another portion of the auxiliary voltage line VL-R may be connected to a second initialization voltage line VL-B through a second contact hole CNT2. Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Cha with the invention of Choi by connecting the initialization voltage line to the auxiliary voltage line directed through a contact hole via a single insulating layer, as in fig. 9A of Cha, or connect the initialization voltage line to the auxiliary voltage line via a mediation metal layer (see fig. 9B of Cha), as taught by Cha, which constitutes combining prior art elements according to known methods to yield predictable results. Regarding claim 3 , Cha is further relied upon to teach wherein the via hole at least penetrates a first gate insulating layer and a second gate insulating layer located between the initialization signal line pattern and the first auxiliary signal line pattern ( see, for example, fig. 9B-via holes (CNT1, CNT2) penetrate two insulating layers (IL4 and IL5) to respectively connect initialization voltage lines (VL-A, VL-B) to auxiliary VL-R ). Regarding claim 14 , Cha discloses wherein the first auxiliary signal line patterns corresponding to the sub-pixel areas in the same row of sub-pixel areas form an integral structure ( see, for example, fig. 3 with description in, for example, [col. 3, ll. 38-52]-pixel conductive pattern 192 (first auxiliary signal lines) may be bent along edge of adjacent pixel electrodes and may include a straight part (192a, 192b, and 192c) and an oblique part 193 (together forming an integral structure) that are alternately arranged ). Regarding claim 15 , Cha discloses a display device comprising the display panel according to claim 1 ( an organic light emitting diode (OLED) display device-see [col. 2, ll. 39-40] ). Regarding claim 16 , Choi discloses a method of manufacturing a display panel ( an organic light emitting diode display device-see figs. 1-15 and [col. 2, ll. 39-41] ), wherein the display panel comprises a plurality of sub-pixel areas arranged in an array, and the plurality of sub- pixel areas are formed as a plurality of rows of sub-pixel areas arranged in sequence along a second direction, each row of sub-pixel areas comprises a plurality of sub-pixel areas arranged along a first direction, and the first direction intersects the second direction ( i.e., a plurality of pixels that may display a predetermined color, for example, the plurality of pixels may include red (R), green (G), and blue (B) pixels disposed in a row direction (first direction) and arranged in a column direction (second direction)-see figs. 3 and 9 with description in [col. 7, ll. 38-47] ); the method comprises: forming an initialization signal line layer ( initialization voltage line 159-see fig. 7 ) and a first auxiliary signal line layer ( pixel conductive pattern 192 (192a, 192b, and 192c)-see figs. 7, 9-13, and 15 with description in [col. 13, ll. 38-52] ) that are stacked in sequence on a substrate along a direction away from the substrate ( i.e., disposed on the passivation layer 180 away from substrate 110-see fig. 7 ); the initialization signal line layer comprises an initialization signal line pattern arranged in each of plurality of the sub-pixel areas ( initialization voltage line 159 corresponding to each pixel row-see figs. 3 and 9 ); the first auxiliary signal line layer comprises a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner ( see, for example, fig. 15 and further description in [col. 13, ll. 38-50], wherein the pixel conductive pattern 192 (192a, 192b, and 192c) extends around pixel electrodes (191a, 191b, and 191c) for each row of pixels ), and the first auxiliary signal line pattern is coupled to the initialization signal line pattern in the corresponding sub-pixel area ( see figs. 3-6 with description in [col. 13, ll. 51-52], and [col. 16, ll. 37-42], wherein it is disclosed that the pixel conductive pattern 192 may transmit the initialization voltage Vint (col. 13, ll. 51-52) … passivation layer 180 includes a contact hole 88 (see fig. 9) disposed on the connector 175. The pixel conductive pattern 192 may transmit the initialization voltage Vint and may be electrically connected to the connector 175 through the contact hole 88 (col. 16, ll. 37-42] and fig. 15) ; at least part of the first auxiliary signal line pattern extends along the first direction ( straight part (192a, 192b, and 192c) extend to be mainly parallel to scan lines (151, 152, and 154)-see [col. 13, ll. 42-43]), i.e., extend along the first direction ), and in a same row of sub-pixel areas, the first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas are sequentially coupled ( the pixel conductive pattern 192 for each row of pixels is an integrated line-see figs. 3 and 9 ). Choi does not appear to expressly disclose wherein there is a third overlapping area between an orthographic projection of the first auxiliary signal line pattern on the substrate and an orthographic projection of the initialization signal line pattern on the substrate, the first auxiliary signal line pattern is directly coupled to the initialization signal line pattern through a via hole located in the third overlapping area. Cha, in for example, fig. 9A with further description in [col. 21, ll. 53-65], illustrates a cross-sectional area of a display device taken along a line IX-IX’ of fig. 8A, wherein a portion of an auxiliary voltage line VL-R may be connected to a first initialization voltage line VL-A through a first contact hole CNT1, similarly, another portion of the auxiliary voltage line VL-R may be connected to a second initialization voltage line VL-B through a second contact hole CNT2. Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Cha with the invention of Choi by connecting the initialization voltage line to the auxiliary voltage line directed through a contact hole via a single insulating layer, as in fig. 9A of Cha, or connect the initialization voltage line to the auxiliary voltage line via a mediation metal layer (see fig. 9B of Cha), as taught by Cha, which constitutes combining prior art elements according to known methods to yield predictable results . 07-21-aia AIA Claim s 2, 10, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Cha, and further in view of Oh et al. (US Patent 11,348,992), hereinafter Oh . Regarding claim 2 , Choi discloses wherein the display panel further comprises a transistor structure ( see figs. 1 and 3-18 ). However, Choi in view of Cha does not appear to expressly teach, the initialization signal line pattern and an active layer in the transistor structure are arranged at a same layer . Oh is relied upon to teach wherein the display panel further comprises a transistor structure, the initialization signal line pattern and an active layer in the transistor structure are arranged at a same layer ( see fig. 4B with description in [col. 12, ll. 65-col. 13, ll. 4], which teaches an initialization voltage line 103 that may include a same material and be arranged in a same layer as a semiconductor layers A1 through A7 (of fourth and 7 thin-film transistors (T4, T7-see fig. 3)) ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Oh with the inventions of Choi and Cha by forming the initialization voltage line on a same layer as an active layer of transistors, as taught by Oh, which constitutes combining prior art elements according to known methods to yield predictable results. Regarding claim 10 , Oh is further relied upon to teach further comprising: a gate line pattern and a reset signal line pattern arranged in each of the plurality of sub-pixel areas, a gate line pattern in a current sub-pixel area and a reset signal line pattern in a next sub-pixel area adjacent along the second direction form an integral structure ( see, for example, fig. 3 with further description in [col. 6, ll. 39-45], which teaches that signal lines 121, 131-133, and 151 or/and initialization voltage line 103 may be shared by neighboring pixels ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Oh with the inventions of Choi and Cha by using common lines to provide signals to adjacent pixels, as taught by Oh, in order to realize high quality and high resolution of display apparatuses (see [col. 1, ll. 31-35]) by minimizing the number of lines used. Regarding claim 11 , Oh is further relied upon to teach wherein the initialization signal line pattern and the active layer in the transistor structure are made of a same material ( see fig. 4B with description in [col. 12, ll. 65-col. 13, ll. 4], which teaches an initialization voltage line 103 that may include a same material and be arranged in a same layer as a semiconductor layer A1 through A7 ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Oh with the inventions of Choi and Cha by forming the initialization voltage line to include a same material as an active layer of transistors, as taught by Oh, which constitutes combining prior art elements according to known methods to yield predictable results. Regarding claim 13 , Choi discloses wherein the first auxiliary signal line layer is located on a side of the initialization signal line layer away from the substrate ( see, for example, fig. 3, wherein, pixel conductive pattern 192 is disposed on passivation layer 180, which is on a side of the initialization voltage line 159 away from the substrate 110 ). Choi does not appear to expressly disclose the initialization signal line layer is made by using an active layer in the display panel. Oh is relied upon to teach the initialization signal line layer is made by using an active layer in the display panel ( see fig. 4B with description in [col. 12, ll. 65-col. 13, ll. 4], which teaches an initialization voltage line 103 that may include a same material and be arranged in a same layer as a semiconductor layers A1 through A7 (of fourth and 7 thin-film transistors (T4, T7-see fig. 3)) ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Oh with the inventions of Choi and Cha by forming the initialization voltage line to include a same material as an active layer of transistors, as taught by Oh, which constitutes combining prior art elements according to known methods to yield predictable results. Choi in view of Oh does not appear to expressly teach and the first auxiliary signal line layer is made by using a second gate metal layer in the display panel. Cha is further relied upon to teach and the first auxiliary signal line layer is made by using a second gate metal layer in the display panel ( see, for example, figs. 7A and 9A-auxiliary signal lines VL_A and VL_B on first interlayer insulating layer IL3 ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Cha with the inventions of Choi and Oh such that the first auxiliary signal line layer is made using existing material on a display layer, such as a second gate metal layer, as taught by Cha, which constitutes combining prior art elements according to known methods to yield predictable results . 07-21-aia AIA Claim 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Cha, and further in view of Kang et al. (US Pub. 2021/0193775), hereinafter Kang . Regarding claim 5 , Choi discloses Choi discloses wherein the display panel further includes a power signal line layer and a data line layer ( the display device may further include a third conductive layer including a data line 171 and a driving voltage line 172 (to transmit driving voltage ELVDD)-see figs. 1 and 3-4, also [col. 4, ll. 26-31] and [col. 8, ll. 30-41] ); the power signal line layer includes a power signal line pattern located in each of the plurality of sub-pixel areas ( see fig. 9 ), and at least part of the power signal line pattern extends along the second direction ( driving voltage line 172 extends in a column direction (second direction)-see fig. 4 ); the data line layer includes a data line pattern located in each of the plurality of sub-pixel areas ( data line 171-see figs. 1 and, 3-4, and 9 ), and at least part of the data line pattern extends along the second direction ( data line extends in a column direction-see fig. 9 ). Choi in view of Oh does not appear to expressly disclose wherein the display panel further includes a power signal line layer and a data line layer that are sequentially stacked on the first auxiliary signal line layer along a direction away from the substrate ; in the same sub-pixel area, an orthographic projection of the power signal line pattern on the substrate overlaps an orthographic projection of the data line pattern on the substrate. Kang is relied upon to teach wherein the display panel further includes a power signal line layer and a data line layer that are sequentially stacked on the first auxiliary signal line layer along a direction away from the substrate ( power supply voltage line PL and data line DL are sequentially stacked on different layers away from the substrate-see fig. 11 ); in the same sub-pixel area, an orthographic projection of the power signal line pattern on the substrate overlaps an orthographic projection of the data line pattern on the substrate ( see, for example, fig. 11, which illustrates a data line DL disposed on a fifth insulating layer 115, a power supply voltage line PL disposed on a third insulating layer 113, wherein the data line DL and the power supply voltage line PL overlap in plan view ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kang with the inventions of Choi and Oh such that a data line and a power supply line are disposed on different insulating layers such that they overlap in plan view, as taught by Kang, in order to minimize electrical signal interference between the power supply line PL and the data line DL (see [0141]) . 07-21-aia AIA Claim s 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Cha, and further in view of Oh as in claim 2, and further in view of Park et al. (US Patent 11,600,688), hereinafter Park . Regarding claim 6 , Choi discloses wherein the display panel further comprises: a power supply signal line layer located on a side of the initialization signal line layer away from the substrate ( third conductive layer includes a driving voltage line 172 (see [col. 8, ll. 30-35]), while the initialization voltage line 159 is part of a second conductive layer (see [col. 8, ll. 6-9]) ), wherein the power supply signal line layer comprises a power signal Line pattern arranged in each of the plurality of sub-pixel areas, at least part of the power signal line pattern extends along the second direction ( see figs. 2-3, wherein the driving voltage line 172 (ELVDD) extends in a column direction (second direction) ). Choi in view of Park and Oh does not appear to expressly teach a third auxiliary signal line layer located between the initialization signal line layer and the power supply signal line layer, wherein the third auxiliary signal line layer comprises a third auxiliary signal line pattern located in each of the plurality of sub- pixel areas, at least part of the third auxiliary signal line pattern extends along the first direction; in the same sub-pixel area, there is a fourth overlapping area between an orthographic projection of the third auxiliary signal line pattern on the substrate and an orthographic projection of the power signal line pattern on the substrate, and the third auxiliary signal line pattern is coupled to the power signal line pattern in the fourth overlapping area; third auxiliary signal line patterns in a same row of sub-pixel areas along the first direction are sequentially coupled. Park, in for example, fig. 6B with description in [col. 14, ll. 56-col. 15, ll. 29], illustrates a driving voltage metal layer (first voltage metal layer 111d) connected to a driving voltage line 172 via a connection member 115a (included in a first conductive layer) through a contact hole 11d passing through insulating layers (160, 120), and the connecting member 115a may be connected to the first voltage metal layer 111d through another contact hole passing through another insulating layer 112, wherein, in plan view, the first voltage metal layer 111d overlaps the driving voltage line 172. Choosing a specific location within the insulating layers for the driving voltage arrangement simply amounts to routine, conventional activity, and a matter of design choice. Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the driving voltage arrangement of fig. 6B of Park with the inventions of Choi, Cha and Oh, wherein, the driving voltage is connected to an auxiliary line via an intermediate connection pattern (e.g., 115a), and wherein the driving voltage layer, the intermediate connection pattern, and the auxiliary line are disposed on different layers and connected to each other via through holes, as taught by Park, in order to reduce signal resistance (see col. 9, ll. 59-62]). Regarding claim 8 , Choi discloses wherein the display panel further comprises a transistor structure ( first transistor T1-see figs. 1 and 8 ) and a storage capacitor ( storage capacitor Cst-see figs. 1 and 8 ), and the storage capacitor includes a first electrode plate ( 155a-see fig. 8 ) and a second electrode plate opposite to each other ( 157-see fig. 8 ), the first electrode plate is located between the substrate and the second electrode plate ( see fig. 8 ), and the first electrode plate and a gate electrode of the transistor structure are arranged at a same layer and made of a same material ( driving gate electrode 155a serves as first electrode of the storage capacitor Cst-see fig. 8 and [col. 12, ll. 53-63] ). Choi in view of Oh does not appear to expressly disclose the first auxiliary signal line layer and/or the third auxiliary signal line layer are arranged at a same layer and made of a same material as the second electrode plate. Park is further relied upon to teach the first auxiliary signal line layer and/or the third auxiliary signal line layer are arranged at a same layer and made of a same material as the second electrode plate ( see, for example, fig. 9, wherein storage capacitor Cst is formed between a gate electrode 155 (first electrode), and a second electrode 175 disposed in the same layer and made of the same material as driving voltage line 172 (172a) ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Park with the inventions of Choi, Cha, and Oh such that the first auxiliary signal line layer a and/or the third auxiliary signal line layer are arranged at a same layer and made of a same material as the second electrode plate, as taught by Park, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., using existing metal layers to form a storage capacitor) . 07-21-aia AIA Claim 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Cha, and further in view of Xin et al. (US Patent 10,516,015), hereinafter Xin . Regarding claim 9 , Choi discloses wherein the display panel further comprises: a gate line layer ( gate electrode layer 155 (155a-155g)-see fig. 10 ), wherein the gate line layer includes a gate line pattern located in each of the plurality of sub-pixel areas, and at least part of the gate line pattern extends along the first direction ( see figs. 9-10, scan line 151 ); a data line layer, wherein the data line layer includes a data line pattern located in each of the plurality of sub-pixel areas, at least part of the data line pattern extends along the second direction ( data line 171 extends in a column direction (second direction)-see figs. 3-4 and 9 ), and an orthographic projection of the data line pattern on the substrate overlaps an orthographic projection of the gate line pattern on the substrate ( each data line 171 (Dm) at least partially overlaps portions of the gate line 155-see figs. 3-4 and 9 ); and a fourth conductive connection portion located in each of the plurality of sub-pixel areas ( connector 174-see fig. 8 ); sub-pixel driving circuits corresponding to the plurality of sub-pixel areas in a one-to-one manner ( subpixel circuits corresponding to subpixels RGB-see figs. 1, 3, and 4-9 ), each of the plurality of sub-pixel driving circuits includes: a driving transistor ( T1-see fig. 1 ), a storage capacitor ( Cst-see fig. 1 ), a first transistor ( T2-see fig. 1 ) and a second transistor ( T3-see fig. 1 ); a gate electrode of the driving transistor is multiplexed as a first electrode plate of the storage capacitor ( gate electrode 155a-see fig. 8 with description in [col. 12, ll. 53-63] ), and the gate electrode of the driving transistor is coupled to a second electrode of the second transistor through the fourth conductive connection portion in the corresponding sub-pixel area ( driving gate electrode 155a is coupled to drain region 137c_1 of T3 via a connector 174 (fourth conductive connection portion)-see fig. 8 ); a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to the gate line pattern in the corresponding sub-pixel area i.e., gate electrodes of T1 and T3 receive the same signal GWn provided via scan line 151, which is part of the gate electrode pattern (see fig. 8). Choi in view of Cha does not appear to expressly disclose a conductive connection portion layer, wherein the conductive connection portion layer includes a third conductive connection portion; the second electrode plate of the storage capacitor is coupled to a second electrode of the first transistor through the third conductive connection portion in the corresponding sub-pixel area; and an orthographic projection of the gate line pattern on the substrate does not overlap an orthographic projection of the third conductive connection portion on the substrate, and/or the orthographic projection of the gate line pattern on the substrate does not overlap an orthographic projection of the fourth conductive connection portion on the substrate. Xin is relied upon to teach a conductive connection portion layer, wherein the conductive connection portion layer includes a third conductive connection portion ( see figs. 2-4 and 7, wherein first connection line L1 representing node N3 is herein equated to the claimed third conductive connection portion ); the second electrode plate of the storage capacitor is coupled to a second electrode of the first transistor through the third conductive connection portion in the corresponding sub-pixel area ( see figs. 2-4 and 7, wherein the first electrode plate C1 of capacitor C is defined as third node N3, and the first connection line L1 is configured to extend to the position at which the first electrode plate C1 of the capacitor is located, which is the same node in which drain electrode T34 of the third transistor T3 is electrically connected to the first electrode C1 of the capacitor C ); and an orthographic projection of the gate line pattern on the substrate does not overlap an orthographic projection of the third conductive connection portion on the substrate, and/ or the orthographic projection of the gate line pattern on the substrate does not overlap an orthographic projection of the fourth conductive connection portion on the substrate ( see figs. 2-4 and 7, wherein second connection line L2 representing node N1 (connecting gate of driving transistor Td and source electrode T43 of fourth transistor T4 (equated to claimed second transistor)), does not overlap second scan line S2 (claimed gate line pattern) ). Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Xin with the inventions of Choi and Cha to include third and fourth conductive patterns for connection an electrode of the storage capacitor to a switching transistor and a gate of a driving transistor to a threshold compensation capacitor, as taught by Xin, which constitutes combining prior art elements according to known methods to yield predictable results . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4, 7, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The references of record fail to teach or suggest: “ wherein the first auxiliary signal line pattern comprises a third portion and a fourth portion, the third portion extends along the first direction; wherein in a direction perpendicular to the first direction, a width of the fourth portion is greater than a width of the third portion ; wherein there is the third overlapping area between an orthographic projection of the fourth portion on the substrate and the orthographic projection of the initialization signal line pattern on the substrate”, as recited in claim 4. “ in the same sub-pixel area, the orthographic projection of the third auxiliary signal line pattern on the substrate is located between an orthographic projection of the light-emitting control signal line pattern on the substrate and an orthographic projection of the reset signal line pattern on the substrate ”, as recited in claim 7. “ a gate electrode of the ninth transistor is coupled to a corresponding light-emitting control signal line pattern, a first electrode of the ninth transistor is coupled to the gate electrode of the third transistor, and a second electrode of the ninth transistor is floating ”, as recited in claim 12. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SARDIS F AZONGHA/Primary Examiner, Art Unit 2627 Application/Control Number: 19/286,189 Page 2 Art Unit: 2627 Application/Control Number: 19/286,189 Page 3 Art Unit: 2627 Application/Control Number: 19/286,189 Page 4 Art Unit: 2627 Application/Control Number: 19/286,189 Page 5 Art Unit: 2627 Application/Control Number: 19/286,189 Page 6 Art Unit: 2627 Application/Control Number: 19/286,189 Page 7 Art Unit: 2627 Application/Control Number: 19/286,189 Page 8 Art Unit: 2627 Application/Control Number: 19/286,189 Page 9 Art Unit: 2627 Application/Control Number: 19/286,189 Page 10 Art Unit: 2627 Application/Control Number: 19/286,189 Page 11 Art Unit: 2627 Application/Control Number: 19/286,189 Page 12 Art Unit: 2627 Application/Control Number: 19/286,189 Page 13 Art Unit: 2627 Application/Control Number: 19/286,189 Page 14 Art Unit: 2627 Application/Control Number: 19/286,189 Page 15 Art Unit: 2627 Application/Control Number: 19/286,189 Page 16 Art Unit: 2627 Application/Control Number: 19/286,189 Page 17 Art Unit: 2627 Application/Control Number: 19/286,189 Page 18 Art Unit: 2627 Application/Control Number: 19/286,189 Page 19 Art Unit: 2627
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