DETAILED ACTION
This office action is in response to Application 19/286,422 filed 7/31/2025 that claims priority to CN2023101020599.1 filed 2/1/2023.
Claims 1-20 have been examined.
Acknowledgement is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 2/1/2023. Examiner notes the priority documents to CN2023101020599.1 have been received by the USPTO.
The IDS sent 8/14/2025 and 4/23/2026 have been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Allowable Subject Matter
Claims 7, 11, 12, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 7 and 17, the prior art does not teach “wherein the second size is based on a third size of a contiguous free physical memory and a physical memory requirement of the process” where claim 6 “a first size of the first virtual memory space is equal t a second size of physical memory allocated to the process”. Thus the physical and logical page size is based on the physical memory requirement of the process.
Closest prior art is Porzio US 2023/0195387 that discloses the memory indicates to the requester the desired size. However, the memory controller determines the size of the physical and logical memory, and it is not determined based on the physical memory requirement of the process.
An updated search failed to identify a teaching alone or in combination to teach the claim limitation.
Regarding claim 11, the prior art does not teach “wherein when a first physical memory does not meet a physical memory requirement of the process, the first page table entry further comprises”. This requirement requires the page table entry is dependent upon a physical memory requirement of the process that is not met by a first physical memory. An updated search failed to identify a teaching alone or in combination to teach the claim limitation.
Regarding Claim 12, the claim is objected to as being dependent upon a rejected based claim but would be allowable if rewritten in independent form to depend on 11 if claim 11 is rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recites the limitation "the first information" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Examiner suggests applicant clarify their intentions, such as claiming a first information comprised of a first indication and a second indication.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 9-10, 13-14, 16, and 19-20 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (1)(2) as being anticipated by CSI_0300, an article titled Lecture 13: page Tables and Address Translation for course CSCI0300 offered by Brown University and available online at https://web.archive.org/web/20221210194727/https:/cs.brown.edu/courses/csci0300/2021/notes/l13.html.
Regarding claim 1, CSI_300 teaches A method comprising: creating a page table for the process, (CSI_0300 page 1 lines 507 that teaches page tables are a means (i.e. a method) of managing virtual address to physical address translations). CSI_0300 page 2 line 26 teaches that each process has its own page table. See also CSI_300 page 2 illustration within S2:x86-64 Page Tables and Address Translation that shows each process (Alice and Eve) has a separate 4-level page table.)
wherein the page table is configured to implement translation from a virtual address of the process to a physical address when the process accesses a memory; (CSI_0300 page 1 lines 507 that teaches page tables are a means (i.e. a method) of managing virtual address to physical address translations. See also CSI_000 page 3 lines 1-9 that discloses that the tab les is used when any process (including the Linux kernel) accesses memory).
wherein the page table is an m-level page table, wherein m is a positive integer, (CSI_0300 page 3 line 23 discloses that the Intel x86-64 use a 4-level page table, thus m is positive integer equal to 4.)
wherein the page table comprises a page table entry (CSI_0300 page 2 lines 28-29 discloses the page table contains one or more page table entries.)
wherein the page table entry comprises information indicating a virtual address range, and (CSI_300 page 3 lines 20-35 discloses that 9 bits in space 47-38 of a virtual address will specify one of 512 entries in the level 3 page table, and each entry of the 512 entries represent addresses in the address rage of 0 to 2**39 (i.e. 0 to 0x7,FFFF,FFFF of the address) for the address specified in the 9 bits. )
wherein the virtual address range corresponds to a virtual memory space of the memory. (CSI_0300 page 1 lines 507 that teaches page tables are a means (i.e. a method) of managing virtual address to physical address translations). CSI_0300 page 2 line 26 teaches that each process has its own page table. See also CSI_300 page 2 illustration within S2:x86-64 Page Tables and Address Translation that shows each process (Alice and Eve) has a separate 4-level page table.)
Regarding claim 2, CSI_0300 teaches all of the limitations of claim 1 above. CSI_0300 further teaches further comprising storing the page table. (CSI_0300 page 1 lines 507 that teaches page tables are a means (i.e. a method) of managing virtual address to physical address translations). CSI_0300 page 2 line 26 teaches that each process has its own page table. See also CSI_300 page 2 illustration within S2:x86-64 Page Tables and Address Translation that shows each process (Alice and Eve) has a separate 4-level page table.)
Regarding claim 3, CSI_0300 teaches A method comprising: receiving an access request for a memory and comprising a virtual address of a process; and (CSI_0300 page 3, lines 1-8 and CSI_0300 page 4 lines 4 through 19 teaches the system is processing virtual addresses of a process.)
reading, based on configuration information and the virtual address, a page table entry from a page table corresponding to the process, (CSI_0300 page 4 line 7 teaches at step 2 the system uses the l4 index from the virtual address to get the L3 page table address, thus accesses (i.e. reads) the L4 entry (based on bits 47-39 of the address) to obtain the L3 page table address for the address.)
wherein the configuration information indicates that at least one page table entry in the page table indicating at least one virtual address range, (CSI_300 page 3 lines 20-35 discloses that 9 bits in space 47-38 of a virtual address will specify one of 512 entries in the level 3 page table, and each entry of the 512 entries represent addresses in the address rage of 0 to 2**39 (i.e. 0 to 0x7,FFFF,FFFF of the address) for the address specified in the 9 bits. )
wherein the first virtual address range corresponds to a first virtual memory space. (CSI_300 page 3 lines 20-35 discloses that the address range is 0 to 0x7,FFFF,FFFF within memory space specified with the9 bits in space 47-38 of the virtual address.).
Regarding claim 4, CSI_0300 teaches the limitations of claim 3 above. CSI_0300 further teaches further comprising further reading the first page table entry at a granularity of a quantity of bytes occupied by the first page table entry. (CSI_0300 page 2 line 28 teaches each L4 page table contains an 8-byte entry that is either empty or contains the address of an L3 page table. Thus the system reads an entry based on reading 8 bytes that are the page table entry.)
Regarding claim 6, CSI_0300 teaches the limitations of claim 3 above. CSI_0300 further teaches wherein a first-size of the first virtual memory space is equal to a second size of a physical memory allocated to the process. (CSI_0300 page 1 line 39 and page 4 line 24 discloses both the logical page size is 4096 bytes, thus the first virtual memory space is 4096 bytes and the second physical memory space allocated to the process is also 4096, thus equal in size.)
Regarding claim 9, CSI_0300 teaches the limitations of claim 3 above. CSI_0300 further teaches wherein when the page table comprises an nth-level page table and an (n+1)th level page table and when the first page table entry is in the nth-level page table, the first page table entry further comprises second information indicating a base address of the (n+1)th-level page table, and wherein n is a positive integer less than m. (As noted above, claim 8 is indefinite as 1) m is undefined and not described within the claims and thus not definite, and 2) applicant appears to be intending to claim a m-level page table where the N indicates a given level of the m-level page table, thus appears to claim wherein when the page table comprises an nth page table and an (n+1)th page table and when the first page table entry is in the nth page table, the first page table entry further comprises second information indicating a base address of the (n+1)th page table, and wherein n is a positive integer less than m. CSI_0300 page 2 S2: x86-64 Page Tables and Address Tables figure and page 3 lines 1-40 that teaches a first level page table entry L4 (thus n=1) and a second level page table L3 (thus N=2) where the first page table L4 comprises second information including a pointer to the L3 table (i.e. to the base address of the L3 table).
Regarding claim 10, CSI_0300 teaches the limitations of claim 3 above. CSI_0300 further teaches wherein the first page table entry further comprises type indication indicating that the first page table entry is capable of indicating the first virtual address range. (CSI_0300 page 2, line 24 (S2: x86 Page Tables and Address Translation) though page 3 line 15 discloses that discloses each page table may be empty, or will contain a valid page table value. Thus a non-empty value in the table is an indication the entry is capable of indicating the first address range.)
Regarding claim 13, An apparatus comprising: a memory configured to store program code; and one or more processors coupled to the memory and configured to invoke the program code to cause the apparatus to: (CSI_0300 Page 2, line 24 (S2: x86 Page Tables and Address Translation) through line 30 discloses the implementation may be used in x86-64 computers that are apparatus that maintain page tables for processes that execute on the x86-64 computers.)
The remainder of claim 13 recites limitations described in claim 3 above and thus is rejected based on the teaching and rationale of claim 3 above.
Regarding claim 14, CSI_0300 teaches the limitations of claim 13 above. CSI_0300 further teaches wherein the one or more processors are further configured to invoke the program code to cause the apparatus to (CSI_0300 Page 2, line 24 (S2: x86 Page Tables and Address Translation) through line 30 discloses the implementation may be used in x86-64 computers that are apparatus that maintain page tables for processes that execute on the x86-64 computers.)
The remainder of claim 14 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 16, CSI_0300 teaches the limitations of claim 13 above.
The remainder of claim 16 recites limitations described in claim 6 above and thus is rejected based on the teaching and rationale of claim 6 above.
Regarding claim 19, CSI_0300 teaches the limitations of claim 13 above.
The remainder of claim 19 recites limitations described in claim 9 above and thus is rejected based on the teaching and rationale of claim 9 above.
Regarding claim 20, CSI_0300 teaches the limitations of claim 13 above. CSI_0300 further teaches wherein the first page table entry further comprises type indication information indicating that the first page table entry is capable f indicating a first virtual address range. (CSI_0300 page 2, line 24 (S2: x86 Page Tables and Address Translation) though page 3 line 15 that discloses each page table may be empty, or will contain a valid page table value. Thus a non-empty value in the table is an indication the entry is capable of indicating the first address range and thus comprises a type indication.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 8, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over CSI_0300, an article titled Lecture 13: page Tables and Address Translation for course CSCI0300 offered by Brown University and available online at https://web.archive.org/web/20221210194727/https:/cs.brown.edu/courses/csci0300/2021/notes/l13.html and further in view of Wu (Wu US 7,895,410 B1 published Feb 22, 2011).
Regarding claim 5, CSI_0300 teaches the limitations of claim 3 above. CSI_0300 further teaches further comprising: determining that the virtual address belongs to the first virtual address range; and (CSI_0300 page 2 line 28 and page 4 lines 4-19 that teaches the system verifies that the entry identified by the 9L4 bits in the virtual address is not empty (i.e. belongs to the first virtual address range).)
determining, based on page offset information (CSI_0300 page 3, lines 20-35 discloses an offset field of 12 bits used to determine where within a page the address starts.) and most significant bit offset information that are in the first page table entry, (CSI_0300 page 3 lines 20-35 discloses the L4 field contains 9 bits that are the most significant bits being used is used to determine the L3 page table entry for the address.) a physical address corresponding to the virtual address, (CSI_0300 page 3 lines 20-35 discloses the L4 field along with the offset are used to translate a virtual address to a physical address.)
wherein the page offset information indicates an offset between a physical start address of a physical memory and a start physical address of a physical page, (CSI_0300 page 3 lines 20-35 that discloses the offset field is an offset relative to a 4096 byte physical page.)
wherein the most significant bit offset information indicates the start physical address, (CSI_0300 page 3 lines 20-35 discloses the L4 field contains a pointer to the L3 field which contains a pointer to the L2 field which in turn contains a pointer to the L1 field which is the destination physical address page, thus the L4 filed indicates the start physical address.)
wherein the physical page comprises the physical memory, and (CSI_0300 page 3 lines 20-35 discloses the page is a physical memory page.)
However, CSI_0300 does not explicitly disclose wherein the first page table entry indicates a physical memory size of the physical page.
Wu, of a similar field of endeavor, further discloses
wherein the first page table entry indicates a physical memory size of the physical page. (Wu fig. 3 and col 4 lines 31-53 discloses that each entry in the page table may contain a page size entry that identifies the appropriate page table and size of the page for the entries).
CSI_0300 and Wu are in a similar field of endeavor as both relate to managing address translations using page tables. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the page size in each page table entry as taught by Wu into the solution of CSI_0300 that uses a first table entry to look up a next entry in a page table as taught by CSI_0300. Thus combining prior arts according to known methods to yield predictable results (allowing each page table entry/segment to be seized such that the total age table overhead is optimal in size. See Wu column 4 lines 46-49).
Regarding claim 8, CSI_0300 teaches the limitations of claim 3 above. However, CSI_0300 does not explicitly teach wherein the first information comprises first indication information and second indication information, the first indication information and third indication, or the second indication information and the third indication information, wherein the first indication information indicates a start address of the first virtual address range, wherein the second indication information indicates an end address of the first virtual address range, and wherein the third indication information indicates a span of the first virtual address range.
Wu, of a similar field of endeavor, further teaches wherein the first information comprises first indication information and second indication information, the first indication information and third indication, or the second indication information and the third indication information, wherein the first indication information indicates a start address of the first virtual address range, wherein the second indication information indicates an end address of the first virtual address range, and wherein the third indication information indicates a span of the first virtual address range. (Wu teaches information first indication and third indication. Wu fig. 3 and col 4 lines 31-53 discloses that each entry in the page table may contain a page size entry that identifies the appropriate page table and size of the page for the entries (i.e. the span of the virtual address which is specified in a page) as well as a pointer to a table as well as an offset (a start address)).
CSI_0300 and Wu are in a similar field of endeavor as both relate to managing address translations using page tables. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the page size in each page table entry as taught by Wu into the solution of CSI_0300 that uses a first table entry to look up a next entry in a page table as taught by CSI_0300. Thus combining prior arts according to known methods to yield predictable results (allowing each page table entry/segment to be seized such that the total age table overhead is optimal in size. See Wu column 4 lines 46-49).
Regarding claim 15, CSI_0300 teaches the limitations of claim 13 above. CSI_0300 further teaches wherein the one or more processors are further configured to invoke the program code to cause the apparatus to: (CSI_0300 Page 2, line 24 (S2: x86 Page Tables and Address Translation) through line 30 discloses the implementation may be used in x86-64 computers that are apparatus that maintain page tables for processes that execute on the x86-64 computers.)
The remainder of claim 15 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Regarding claim 18, CSI_0300 teaches the limitations of claim 13 above.
The remainder of claim 18 recites limitations described in claim 8 above and thus is rejected based on the teaching and rationale of claim 8 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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