DETAILED ACTION
Claims 1-20 are pending.
Priority: 5/12/2022(Continuation of 17/663121)
Assignee: Micron
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-30 of U.S. Patent No. 12056061(17/663,121). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious variations of the parent.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 12393524(18/755,382). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious variations of the parent.
19/287,559(Instant)
1. A method, comprising: selecting, based at least in part on a power up condition of a device, a first matrix from among a first set of bijective matrices and a second matrix from among a second set of bijective matrices, wherein each matrix of the first set of bijective matrices is associated with a first size different than a second size associated with each matrix of the second set of bijective matrices; generating a first address of a first address space based at least in part on applying the first matrix and the second matrix to a second address of a second address space; and accessing a memory array of the device based at least in part on generating the first address.
12056061(Parent)
7, 11, 12
Analysis
Claim 12, through claims 11 and 7, selects two matrices on power-up, uses distinct matrix sets, applies the matrices to different address portions, and requires different matrix sizes. Its added nonzero-element and reordering/non-reordering limitations make it a narrower species of instant claim 1.
12393524(Parent)
1
Analysis
Parent claim 1 contains every limitation of instant claim 1 and additionally requires the two matrix sets to exclude one another and applies the matrices to respective first and second address portions. The parent claim is therefore a narrower species fully inside the instant claim.
19/287,559(Instant)
2. The method of claim 1, the method further comprising: accessing the memory array based at least in part on a third address of the first address space; and generating a fourth address of the second address space based at least in part on applying an inverse of the first matrix and an inverse of the second matrix to at least a portion of the third address of the first address space.
12056061(Parent)
8, 12
Analysis
No single parent claim applies inverses to both matrices of claim 12. Claim 8, however, claims inverse transformation for the same address-scrambling operation. Repeating that claimed inverse operation for each of the two matrices is a predictable variation.
12393524(Parent)
2
Analysis
Parent claim 2 adds explicit third and fourth matrices that are inverses of the selected matrices and applies them to recover the second-space address. That implementation satisfies the broader inverse language of instant claim 2.
19/287,559(Instant)
3. The method of claim 1, wherein the first matrix and the second matrix are based at least in part on different portions of a seed value.
12056061(Parent)
10, 12
Analysis
Claim 10 associates two matrices with different seed values, while instant claim 3 uses different portions of one seed. Treating seed segments as the respective selection inputs is a plausible design variation, but the exact same-seed/different-portions limitation is not claimed in this patent.
12393524(Parent)
3
Analysis
Parent claim 3 expressly bases the first and second matrices on different portions of one seed value. Together with its narrower claim 1 base, it falls wholly within instant claim 3.
19/287,559(Instant)
4. The method of claim 1, further comprising: receiving a command that indicates the second address for accessing the memory array; and determining a third address of a third address space based at least in part on the first address, wherein the third address space comprises a physical address space, wherein accessing the memory array is in accordance with determining the third address.
12056061(Parent)
12, 13
Analysis
Claim 13 claims command receipt and conversion to a physical-space address for memory access. Applying that claimed address-space step to the two-matrix, different-size configuration of claim 12 is a predictable use of the same scrambling pipeline.
12393524(Parent)
4
Analysis
Parent claim 4 receives the indicated address, derives a physical-space address from the scrambled address, and accesses memory using that address. The phrase “using” is within instant claim 4’s broader “in accordance with determining” formulation.
19/287,559(Instant)
5. The method of claim 4, wherein the second address comprises a logical address, the method further comprising: determining a fourth address of a fourth address space based at least in part on the first address, and wherein accessing the memory array is in accordance with determining the fourth address.
12056061(Parent)
12, 13
Analysis
The parent claims do not expressly require the additional fourth address of instant claim 5. Claim 13 and the supporting embodiments do teach logical, intermediate, and physical address spaces, making another address-space stage plausible, but this is not a clean anticipation case.
12393524(Parent)
5
Analysis
Parent claim 5 requires a logical second address and a further address derived from the first address for memory access. Its inherited claim 4/1 limitations are narrower than, and fully satisfy, instant claim 5.
19/287,559(Instant)
6. The method of claim 1, wherein the first set of bijective matrices and the second set of bijective matrices each comprise one or more reordering matrices.
12056061(Parent)
7, 11, 12
Analysis
Claim 7 requires reordering matrices in the first set, and claim 11 adds a distinct second set. The parent does not expressly require a reordering matrix in the second set. Symmetric inclusion is plausible, but the missing second-set requirement provides an argument for distinctness.
12393524(Parent)
6
Analysis
Instant claim 6 requires at least one reordering matrix in each set. Parent claim 6 requires both reordering and non-reordering subsets in each set, which necessarily includes the reordering matrices required by the instant claim.
19/287,559(Instant)
7. The method of claim 1, wherein generating the first address comprises: scrambling one or more bits of the second address, wherein accessing the memory array of the device is based on scrambling the one or more bits.
12056061(Parent)
12, 16, 17
Analysis
The claimed matrix transformation generates an address from address bits, and claims 16-17 expressly claim bitwise combinatorial multiplication and summation. Characterizing the resulting operation as scrambling one or more bits is at least an obvious functional description of the same operation.
12393524(Parent)
7
Analysis
The scrambling-one-or-more-bits limitation is materially the same, while parent claim 7 inherits the additional narrowing limitations of parent claim 1.
19/287,559(Instant)
8. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: select, based at least in part on a power up condition of a device, a first matrix from among a first set of bijective matrices and a second matrix from among a second set of bijective matrices, wherein each matrix of the first set of bijective matrices is associated with a first size different than a second size associated with each matrix of the second set of bijective matrices; generating a first address of a first address space based at least in part on applying the first matrix and the second matrix to a second address of a second address space; and access a memory array of the device based at least in part on generating the first address.
12056061(Parent)
7, 11, 12
Analysis
Claim 12 claims the same core two-matrix method. Storing processor instructions to perform that method changes statutory form but not the substantive address-scrambling operation.
12393524(Parent)
8
Analysis
The computer-readable-medium claims track one another, but parent claim 8 additionally requires mutually exclusive matrix sets and respective application to first and second address portions. Parent claim 8 is a narrower species.
19/287,559(Instant)
9. The non-transitory computer-readable medium of claim 8, wherein the instructions are further executable by the one or more processors to: access the memory array based at least in part on a third address of the first address space; and generate a fourth address of the second address space based at least in part on applying an inverse of the first matrix and an inverse of the second matrix to at least a portion of the third address of the first address space.
12056061(Parent)
8, 12
Analysis
Claim 8 claims inverse recovery for the same scrambling process. Encoding that inverse operation for each matrix in claim 12 is a predictable software implementation.
12393524(Parent)
9
Analysis
Parent claim 9’s explicit inverse-matrix determination and reverse transformation satisfy the broader inverse instructions in instant claim 9.
19/287,559(Instant)
10. The non-transitory computer-readable medium of claim 8, wherein the first matrix and the second matrix are based at least in part on different portions of a seed value.
12056061(Parent)
10, 12
Analysis
The difference is again different portions of one seed versus different seed values. The claim set suggests separate seed-based matrix selections, but does not expressly claim partitioning one seed.
12393524(Parent)
10
Analysis
Parent claim 10 expressly uses different portions of a seed value for the two matrices. Its inherited claim 8 limitations are narrower than instant claim 10.
19/287,559(Instant)
11. The non-transitory computer-readable medium of claim 8, wherein the instructions are further executable by the one or more processors to: receive a command that indicates the second address for accessing the memory array; and determine a third address of a third address space based at least in part on the first address, wherein the third address space comprises a physical address space, wherein accessing the memory array is in accordance with determining the third address.
12056061(Parent)
12, 13
Analysis
Claim 13 supplies the command and physical-address access step. Implementing that step in code for claim 12’s two-matrix transformation is a predictable class and implementation change
12393524(Parent)
11
Analysis
Parent claim 11’s command, physical-space address, and access using that address fall within instant claim 11’s corresponding functional language.
19/287,559(Instant)
12. The non-transitory computer-readable medium of claim 11, wherein the second address comprises a logical address, and the instructions are further executable by the one or more processors to: determine a fourth address of a fourth address space based at least in part on the first address, wherein the third address space comprises an intermediate address space, wherein accessing the memory array is in accordance with determining the fourth address.
12056061(Parent)
12, 13
Analysis
The issued claims omit the additional fourth-address requirement. The logical/intermediate/physical embodiments support a predictable staged translation argument, but instant claim 12 retains a meaningful limitation absent from the parent claims.
12393524(Parent)
12
Analysis
Parent claim 12 adds the logical-address and further-address limitations and uses the further address for access. The added statement that the third space is intermediate does not remove it from the broader scope of instant claim 12.
19/287,559(Instant)
13. The non-transitory computer-readable medium of claim 8, wherein the first set of bijective matrices and the second set of bijective matrices each comprise one or more reordering matrices.
12056061(Parent)
7, 11, 12
Analysis
The first set expressly includes reordering matrices, but the second set is not expressly required to do so. Requiring both sets to include a reordering option is plausible symmetry, yet it remains a claim-level difference.
12393524(Parent)
13
Analysis
Parent claim 13 requires reordering and non-reordering subsets in both matrix sets; that necessarily satisfies instant claim 13’s requirement for one or more reordering matrices in each set.
19/287,559(Instant)
14. The non-transitory computer-readable medium of claim 8, wherein the instructions to generate the first address are executable by the one or more processors to: scramble one or more bits of the second address, wherein accessing the memory array of the device is based on scrambling the one or more bits.
12056061(Parent)
12, 16, 17
Analysis
The parent’s claimed matrix operations act on address bits; claims 16-17 expressly implement the transformation bitwise. Code that “scrambles” those bits is an obvious software expression of the claimed operation.
12393524(Parent)
14
Analysis
The bit-scrambling instruction is substantively the same, and parent claim 14 inherits a narrower independent claim.
19/287,559(Instant)
15. An apparatus, comprising: processing circuitry associated with one or more memory devices and configured to cause the apparatus to: select, based at least in part on a power up condition of a device, a first matrix from among a first set of bijective matrices and a second matrix from among a second set of bijective matrices, wherein each matrix of the first set of bijective matrices is associated with a first size different than a second size associated with each matrix of the second set of bijective matrices; generating a first address of a first address space based at least in part on applying the first matrix and the second matrix to a second address of a second address space; and access a memory array of the device based at least in part on generating the first address.
12056061(Parent)
12, 15,
Analysis
Claim 12 supplies the two-matrix, different-size process, while claim 15 claims circuitry performing the same class of matrix-based address transformation. Implementing claim 12 with processing circuitry is a predictable apparatus form.
12393524(Parent)
15
Analysis
The apparatus claims track one another, but parent claim 15 additionally requires mutually exclusive sets and applies the matrices to respective address portions. It is a narrower apparatus species.
19/287,559(Instant)
16. The apparatus of claim 15, wherein the processing circuitry is further configured to cause the apparatus to: access the memory array based at least in part on a third address of the first address space; and generate a fourth address of the second address space based at least in part on applying an inverse of the first matrix and an inverse of the second matrix to at least a portion of the third address of the first address space.
12056061(Parent)
12, 18
Analysis
Claim 18 claims apparatus circuitry using an inverse matrix to recover an address. Extending that inverse circuitry to each matrix in claim 12’s two-matrix configuration is a predictable duplication.
12393524(Parent)
16
Analysis
Parent claim 16 explicitly determines inverse matrices and performs the reverse address transformation, satisfying the broader inverse functionality in instant claim 16.
19/287,559(Instant)
17. The apparatus of claim 15, wherein the first matrix and the second matrix are based at least in part on different portions of a seed value.
12056061(Parent)
10, 15, 17
Analysis
The parent claims seed-based circuit selection and different seed values for two matrices, but not different portions of one seed in the two-size configuration. The seed partition supplies a possible distinction, although it appears to be a routine input-allocation choice.
12393524(Parent)
17
Analysis
Parent claim 17 expressly derives the two matrices from different seed portions. With its narrower claim 15 base, it falls wholly within instant claim 17.
19/287,559(Instant)
18. The apparatus of claim 15, wherein the processing circuitry is further configured to cause the apparatus to: receive a command that indicates the second address for accessing the memory array; and determine a third address of a third address space based at least in part on the first address, wherein the third address space comprises a physical address space, wherein accessing the memory array is in accordance with determining the third address.
12056061(Parent)
12, 19, 30
Analysis
Claims 19 and 30 claim apparatus receipt of an address command and physical-address generation. Adding that claimed circuitry to claim 12’s two-matrix operation is a predictable combination within the same address pipeline.
12393524(Parent)
18
Analysis
Parent claim 18 receives the command, derives a physical-space address, and accesses memory using it. Those operations satisfy instant claim 18.
19/287,559(Instant)
19. The apparatus of claim 18, wherein the second address comprises a logical address, wherein the processing circuitry is further configured to cause the apparatus to: determine a fourth address of a fourth address space based at least in part on the first address, and wherein accessing the memory array is in accordance with determining the fourth address.
12056061(Parent)
12, 19, 30
Analysis
The parent apparatus claims do not require the fourth address. Logical/intermediate/physical embodiments make staged translation plausible, but the extra address remains the best claim-level distinction from this patent.
12393524(Parent)
19
Analysis
Parent claim 19 requires a logical second address and a further address derived from the first address for memory access. It is within the broader scope of instant claim 19.
19/287,559(Instant)
20. The apparatus of claim 15, wherein the first set of bijective matrices and the second set of bijective matrices each comprise one or more reordering matrices.
12056061(Parent)
7, 11, 12
Analysis
The parent claims place reordering and non-reordering matrices in the first set and claim two sets of different sizes, but do not expressly put a reordering matrix in the second set. That symmetric requirement is plausibly obvious but not anticipated
12393524(Parent)
20
Analysis
Parent claim 20 requires both reordering and non-reordering subsets in each matrix set. That narrower configuration necessarily includes the reordering matrices required by instant claim 20.
Allowable Subject Matter
Claim(s) 1-20 contain allowable matter based on the prior art.
The following is an examiner’s statement of reasons for allowance. Claim(s) 1, 8, 15 each contain the following limitations that distinguish from the prior art:
“…selecting, based at least in part on a power up condition of a device, a first matrix from among a first set of bijective matrices and a second matrix from among a second set of bijective matrices, wherein each matrix of the first set of bijective matrices is associated with a first size different than a second size associated with each matrix of the second set of bijective matrices; generating a first address of a first address space based at least in part on applying the first matrix and the second matrix to a second address of a second address space; and accessing a memory array of the device based at least in part on generating the first address.…”(claim 1),
“…select, based at least in part on a power up condition of a device, a first matrix from among a first set of bijective matrices and a second matrix from among a second set of bijective matrices, wherein each matrix of the first set of bijective matrices is associated with a first size different than a second size associated with each matrix of the second set of bijective matrices; generating a first address of a first address space based at least in part on applying the first matrix and the second matrix to a second address of a second address space; and access a memory array of the device based at least in part on generating the first address.…”(claim 8),
“… select, based at least in part on a power up condition of a device, a first matrix from among a first set of bijective matrices and a second matrix from among a second set of bijective matrices, wherein each matrix of the first set of bijective matrices is associated with a first size different than a second size associated with each matrix of the second set of bijective matrices; generating a first address of a first address space based at least in part on applying the first matrix and the second matrix to a second address of a second address space; and access a memory array of the device based at least in part on generating the first address…”(claim 15).
A related prior art is Bhargava et al.(20180150389) where the address adder operates on a portion of the entire address, such as the most significant bits (MSBs) to reduce complexity and minimize adder delay overhead. The process of wear leveling is designed to reduce the premature failure in memory arrays by preventing any one region of memory is used much more frequently than any other region.
Another related prior art is Van Dyke et al.(20160062910) where the method involves generating a first potential hash value, and thus enhances the overall performance of the computer system, enables an efficient tuning of the associated memory address mapping, enables to distribute the data within the memories in an efficient way, reduces the cache hotspotting for input patterns of powers of two, and also reduces the cache hotspotting for input patterns of non-powers of two.
The claims above therefore distinguish from the disclosures of the most relevant prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights