DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Fig. 6 includes a mislabeled path. Specifically, step 415 of Fig. 6 has a clear “NO” path and another path that is likely supposed to be labeled as “YES”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 – 6 and 8 – 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 8 recite the limitations "the respective follower epochs" and “the same leader epoch” in line 2 (both claims). There is insufficient antecedent basis for this limitation in the claim. “A respective follower epoch” nor “A same leader epoch” were previously identified. The dependent claims inherit and do not correct this problem.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, and 7 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US Patent Application Publication No. 2020/0201570 (herein after referred to as Kim).
Regarding claims 1, 7, and 10, Kim describes a computer device [a method] [a non-transitory computer-readable recording medium (…the inventive concepts may be embodied as a system, method, computer program product, and/or a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon… (page 9, paragraph [0125]))] for updating a dual-order-guaranteed mapping table, the computer device comprising: a storage (The storage device 300 may include… a plurality of nonvolatile memories 320a, 320b and 320c, and a buffer memory 330… (page 4, paragraph [0048])); and a processor configured to connect to the storage (The storage controller 310 may control an operation of the storage device 300, e.g., a data write operation based on a command, an address, and data that are received from the host 200 (page 4, paragraph [0049])), and to execute at least one instruction stored in the storage, wherein the processor comprises: a storage controller (Storage controller 310 (page 4, paragraph [0048]) and Fig. 2) configured to detect a write command indicating order constraints of write requests for two streams (The first write data may correspond to a first write command and a first stream, and may have first logical addresses which are successive addresses… The second write data may correspond to a second write command and a second stream, and may have second logical addresses which are successive addresses. The second write command may be subsequent to the first write command, and may be received after the first write command is received. The second stream may be different from the first stream. The second buffer group may be different from the first buffer group (page 4, paragraph [0060]). …to ensure the data write order from the host independently of the control of the host, the multi-stream buffer operating scheme may be implemented by determining the continuity of the logical addresses, without or rather than receiving a stream identifier (ID) from the host, according to some example embodiments… logical addresses of write data in the same stream may be consecutive, and logical addresses of write data in different streams may be non-consecutive. Thus, write data having consecutive logical addresses may be determined as the same stream, and may be assigned to the same buffer group (page 5, paragraph [0062]). …the first serial numbers may sequentially increase in accordance with an order of the first write data, and the second serial numbers may sequentially increase in accordance with an order of the second write data… (page 6, paragraph [0072])), to generate a mapping table for epochs of the streams based on the write command (A logical-to-physical mapping table is updated based on the plurality of serial numbers (operation S500). As described above, the plurality of serial numbers [epoch] may indicate the data write order provided from the host. Thus, when the logical-to-physical mapping table is updated based on the plurality of serial numbers, the data write order from the host may be ensured regardless of a program order in operation S400. The update operation in operation S500 will be described with reference to Fig. 12 and the like (page 3, paragraph [0041]). …by assigning the serial numbers at the time of buffer assigning operation and by updating the mapping table based on the assigned serial numbers. In other words, the data write order from the host may be ensured or guaranteed even if there is no direct control from the host… (page 3, paragraph [0043]). The host 200 provides a plurality of data write commands WCMD… to the storage device 300 (page 3, paragraph [0047])), and to record the streams in the storage according to the order constraints using the mapping table (The plurality of write data temporarily stored in the plurality of buffer groups are programmed into a plurality of memory blocks (operation S400). …the plurality of write data may be programmed based on the multi-stream scheme, and data temporarily stored in a buffer group which is full (e.g., is entirely filled) first may be performed first… (page 3, paragraph [0040]). …when updating the logical-to-physical mapping table (operation S500), it may be determined or judged first whether an update condition is satisfied… the update condition may include whether the program operation is performed, the number of programmed write data, the number of serial numbers included in a meta log tree and/or a delay meta log, or the like (page 7, paragraph [0094]). …the update operation may be performed in consideration of the serial numbers indicating the data write order when the address information are reflected in the logical-to-physical mapping table (page 9, paragraph [0114])); and a flash translation layer configured to update the mapping table with mapping information of each epoch (…each of the plurality of nonvolatile memories 320a, 320b and 320c may include a NAND flash memory (page 4, paragraph [0053]). …when updating the logical-to-physical mapping table (operation S500), it may be determined or judged first whether an update condition is satisfied (operation S510). For example, the update condition may include whether the program operation is performed, the number of programmed write data, the number of serial numbers included in a meta log tree and/or a delay meta log, or the like (page 7, paragraph [0094]). When the reference serial number and the first serial number are consecutive (operation S520: YES), address information of the first write data may be updated to or in a meta log tree (operation S530)… (page 8, paragraph [0096]). Address mapping related to NAND flash memory is translation of flash).
Regarding claims 2 and 8, Kim describes the computer device of claim 1 [the method of claim 7] (see above), wherein the storage controller is configured to generate delayed mapping entries for the respective follower epochs after the same leader epoch corresponding to each of the streams, and the delayed mapping entries have sibling fields into which mutual addresses are entered, respectively (When the reference serial number and the first serial number are non-consecutive (operation S520: NO), the address information of the first write data may be added to or in a delayed meta log (operation S540) (page 8, paragraph [0097]). After the address information of the first write data is added to the delayed meta log, a second serial number of second write data programmed in the memory block and included in the delayed meta log may be compared with the reference serial number (operation S550). The second serial number may be the smallest serial number among serial numbers of write data programmed in the memory block and included in the delay meta log (page 8, paragraph [0098]). The two serial numbers may be non-consecutive, and thus address information of the write data D1 to D16 may not be updated to the meta log tree MLT and may be added to a delay meta log DML (page 8, paragraph [0106])).
Regarding claims 3 and 9, Kim describes the computer device of claim 2 [the method of claim 8] (see above), wherein the storage controller is configured to transmit the epochs to a write buffer in order in which the epochs are serviced, to be transmitted from the write buffer to the storage according to the order constraints, and the flash translation layer is configured to, when the follower epoch is transmitted for each stream, add mapping information of the follower epoch to a delayed mapping entry for the follower epoch, and when the leader epoch is transmitted after the follower epoch is transmitted, update the mapping table with mapping information of the leader epoch and the mapping information of the follower epoch (When the reference serial number and the first serial number are non-consecutive (operation S520: NO), the address information of the first write data may be added to or in a delayed meta log (operation S540) (page 8, paragraph [0097]). After the address information of the first write data is added to the delayed meta log, a second serial number of second write data programmed in the memory block and included in the delayed meta log may be compared with the reference serial number (operation S550). The second serial number may be the smallest serial number among serial numbers of write data programmed in the memory block and included in the delay meta log (page 8, paragraph [0098]). The two serial numbers may be non-consecutive, and thus address information of the write data D1 to D16 may not be updated to the meta log tree MLT and may be added to a delay meta log DML (page 8, paragraph [0106])).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: Claims 4 – 6 are rejected under 35 USC 112(b) as disclosed above. Claim 4 describes, “the computer device of claim 3, wherein the flash translation layer is configured to, when the leader epoch is transmitted after the follower epoch is transmitted, update the mapping table with the mapping information of the leader epoch, identify a sibling field of the delayed mapping entry for the follower epoch, when an address is present in the sibling field, initialize a sibling field of a delayed mapping entry corresponding to the address to a null state, update the mapping table with the mapping information of the follower epoch, and remove the delayed mapping entry of the follower epoch, and when the sibling field is in the null state, update the mapping table with the mapping information of the follower epoch, and remove the delayed mapping entry of the follower epoch. Claim 5 describes, “the computer device of claim 3, wherein the storage controller is configured to set a mappable flag in a logical block of each epoch, the mappable flag is set to TRUE for the leader epoch, set to TRUE for the follower epoch after the leader epoch is transmitted, and set to FALSE for the follower epoch before the leader epoch is transmitted, and the flash translation layer is configured to, when the mappable flag is set to FALSE in a logical block of an epoch transmitted from the storage controller to the write buffer, detect mapping information of the epoch in the logical block of the epoch and add the same to a delayed mapping entry of the epoch.” Claim 6 depends from claim 4. Kim does not teach or suggest all of the limitations added in these dependent claims. McWilliams et al. US Patent Application Publication No. 2008/0301256 describes a memory sub-system including a fine-grained memory and a less-fine-grained (e.g., page-based) memory. One of the links of the link field of page information table entry 731.2 indicates that the list of available pages ends by pointing to NULL entry 749. However, McWilliams does not teach or suggest all of the limitations added in the identified dependent claims. Sabol et al. US Patent Application Publication No. 2023/0019966 describes a system for drive placement or placement functionality that enables initial copies of data to be placed on a drive in reclaim units in a manner which probabilistically more efficient from a garbage collection perspective and leverages knowledge of a host or application using the data. However, Sabol does not teach or suggest all of the limitations added in the identified dependent claims. Martineau et al. US Patent Application Publication No. 2017/0235486 describes enhanced multi-streaming through statistical analysis. By saving each streaming page with metadata indicating the stream ID, and the time the page was saved/invalidated, the SSD may calculate the stream’s distribution model and “nominal” data lifetime. However, Martineau does not teach or suggest all of the limitations added in the identified dependent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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August 29, 2026
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