Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 19/290,227 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The first instance of all acronyms or abbreviations should be spelled out for clarity.
In response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by prior art or disclosed by the examiner.
INFORMATION CONCERNING DRAWINGS
The applicant’s drawings submitted are acceptable for examination purposes.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
The instant application no. 19290227 filed 08/04/2025 claims foreign priority to 10-2024-0136083, filed 10/07/2024.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement(s) dated 8/4/2025 is/are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy (copies) of the PTOL-1449(s) initialed and dated by the examiner is/are attached to the instant office action.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 4, the Speciation does not appear to provide written description for the limitations “different commands for each of the first plane, the second plane, and the target plane.” as it appears that target plane information in the command as recited in claim 1 would refer to either the first plane and the second plane. For example, the Specification recites “[0097] The cache latch control logic 2000 may receive a command including target plane information from the memory controller 1200 and selectively initialize the first to fourth cache latches CL1 to CL4. For example, if the command includes first plane information, the cache latch control logic 2000 may provide a first cache latch initialization signal DI1 to the first cache latches CL1 through the first page buffer driver PBD1… 0118] In FIG. 10, the memory device 1100 may load the data loading command 8×h, the column address CA, the row address RA, and the data through the input/output lines IOx. The data loading command 8×h may include target plane information. The data loading command 8×h may be matched one-to-one with each plane. For example, 80 h may be matched with all planes, 81 h may be matched with the first plane, 82 h may be matched with the second plane, 83 h may be matched with the third plane, and 84 h may be matched with the fourth plane. The data loading command may have different commands for each plane…. [0135] In FIG. 18, the cache latch control logic 2000 may receive a data loading command including target plane information during a program operation, and may selectively initialize the first to sixth cache latches CL1 to CL6 according to the target plane information. The data loading command may match the command bits of each input/output line with each plane. The cache latch control logic 2000 may complete the cache latch initialization operation within a limited time, and may reduce the peak current.” Thus, while the Specification provides support for different commands for each plane and a command including target plane information would appear to indicate first plane and second plane to access but a description for a separate command for a target plane has not been found in the Specification. Appropriate correction/clarification is required.
As per claims 5-6,
5. The memory device of claim 3, wherein the command is configured to be one-to-one matched with the first plane, the second plane, and the target plane.
6. The memory device of claim 3, wherein command bits of each input/output line are configured to be matched with the first plane, the second plane, and the target plane.
it appears that the target plane corresponds to the first plane and second plane but it is not separate from the recited first plane and second plane as set forth in claims 5-6; thus, Applicant’s Specification does not provide proper written description for command or command bits for a first plane, a second plane, and the target plane as recited in claims 5-6. For example, the Specification recites “[0118] In FIG. 10, the memory device 1100 may load the data loading command 8×h, the column address CA, the row address RA, and the data through the input/output lines IOx. The data loading command 8×h may include target plane information. The data loading command 8×h may be matched one-to-one with each plane. For example, 80 h may be matched with all planes, 81 h may be matched with the first plane, 82 h may be matched with the second plane, 83 h may be matched with the third plane, and 84 h may be matched with the fourth plane. The data loading command may have different commands for each plane.” But the target plane is not recited as separate. Appropriate correction/clarification is required.
Dependent claims 7-8 are rejected for including the deficiencies of independent claim 6, upon which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-8, 10 and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 4, the limitations “different commands for each of the first plane, the second plane, and the target plane.” render the claim indefinite as it appears that target plane information in the command as recited in claim 1 would refer to either the first plane and the second plane but a separate command does not appear to correspond to the target plane as recited in claim 4. For example, the Specification recites “[0097] The cache latch control logic 2000 may receive a command including target plane information from the memory controller 1200 and selectively initialize the first to fourth cache latches CL1 to CL4. For example, if the command includes first plane information, the cache latch control logic 2000 may provide a first cache latch initialization signal DI1 to the first cache latches CL1 through the first page buffer driver PBD1.” Thus, a command including target plane information would appear to indicate first plane and second plane to access but it does not appear to be a separate command. Appropriate correction/clarification is required.
As per claims 5-6,
5. The memory device of claim 3, wherein the command is configured to be one-to-one matched with the first plane, the second plane, and the target plane.
6. The memory device of claim 3, wherein command bits of each input/output line are configured to be matched with the first plane, the second plane, and the target plane.
it appears that the target plane corresponds to the first plane and second plane but it is not separate from the recited first plane and second plane as set forth in claims 5-6; thus, the limitations referring to the target plane as recited in claims 5 and 6 render the claims indefinite. For example, the Specification recites “[0118] In FIG. 10, the memory device 1100 may load the data loading command 8×h, the column address CA, the row address RA, and the data through the input/output lines IOx. The data loading command 8×h may include target plane information. The data loading command 8×h may be matched one-to-one with each plane. For example, 80 h may be matched with all planes, 81 h may be matched with the first plane, 82 h may be matched with the second plane, 83 h may be matched with the third plane, and 84 h may be matched with the fourth plane. The data loading command may have different commands for each plane.” But the target plane is not recited as separate. Appropriate correction/clarification is required.
Dependent claims 7-8 are rejected for including the deficiencies of independent claim 6, upon which they depend.
As per claims 10 and 16-20, the limitation “n-th” renders the claim indefinite as it is not clear what the values of n are. Thus, metes and bounds of the claims are not clear. Appropriate correction/clarification is required.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US 2022/0122667).
1. A memory device, comprising: a memory cell array including a first plane and a second plane; [Lee teaches “memory cell array 110” (fig. 2 and related text) where “[0068] FIG. 3 is a block diagram illustrating an embodiment of memory device 100, which includes first to fourth planes 105a to 105d, a peripheral circuit 120, and a control logic 130.” Where (fig. 3 and related text) depict first plane 105a and second plane 105b]
a page buffer circuit including first cache latches configured to store data in the first plane and second cache latches configured to store data in the second plane; and [Lee teaches “page buffer group 123” (fig. 2 and related text; par. 0049) where each plane as shown in fig. 3 and related text includes a page buffer circuit 123a, 123b, etc. (fig. 3 and related text; par. 0069) and each page buffer circuit includes latches 1231, 1232, 1233, 1234 and cache latch 1235 (fig. 4a and related text) where “page buffer circuit 1230 may be any one page buffer PBi among the page buffer PB1 to PBn shown in FIG. 2 or 3.” (par. 0071)]
input/output lines configured to receive a command and addresses from a memory controller, [Lee teaches CMD, ADDR, DATA lines in (fig. 2 and related text) where memory controller 200 (fig. 1 and related text) where “[0043] The memory controller 200 may control the memory device 100 to autonomously perform a program operation, a read operation, or an erase operation… [0044] In accordance with an embodiment, the memory controller 200 may provide a multi-plane program command to the memory device 100…”] wherein the command includes target plane information configured to initialize at least one of the first cache latches and the second cache latches [Lee teaches “[0044]… the memory controller 200 may provide a multi-plane program command to the memory device 100. When the memory device 100 receives the multi-plane program command, the memory device 100 may initialize a cache latch, based on the received command and an address, and receive data input to the initialized cache latch. Also, the memory device 100 may perform a multi-plane program operation, based on the command, the address, and the data.” “[0093]… the memory device 100 may receive commands 7-1 and 7-2 and an address 7-3. For example, the memory device 100 may identify that the first sub-command Sub 1 is a multi-plane command (for performing the multi-plane program operation) based on 01h and 80h and may identify that the data to be input is LSB data (corresponding to the LSB page) based on 01h among the received commands. Also, the memory device 100 may identify which plane among the plurality of planes the data to be input is data to be stored in based on ADDR.” (see figs. 7 and 8 and related text) “[0126] When the corresponding program command is the multi-program command (S1220, Yes), the memory device 100 may simultaneously initialize cache latches of a plurality of planes (S1230). In one embodiment, the cache latch may be a latch which receives data to be stored in a memory cell. When an error occurs in the latch receiving the data, data different from that which the host 2000 intends to transfer may be stored. Therefore, the memory device may perform an operation of initializing the cache latch before the cache latch receives data.
[0127] In accordance with an embodiment, when a cache latch corresponding to one plane among the plurality of planes is initialized, the memory device 100 may simultaneously initialize cache latches corresponding to the other planes. For example, the memory device 100 may control a target latch to be initialized by transmitting the cache reset signal CRST to the corresponding target latch. In accordance with an embodiment, in a first address cycle to data loading time tADL (in which a cache latch of a first plane is initialized), the memory device 100 may transmit the cache reset signal CRST to the page buffer group 123 including the other cache latches so that the other cache latches are initialized. That is, the memory device 100 may transmit the cache reset signal CRST to each page buffer including cache latches so that all cache latches are simultaneously initialized.
[0128] Also, the memory device 100 may perform the multi-plane program operation (S1240). For example, when the memory device 100 simultaneously initializes the cache latches of the plurality of planes and receives the entire multi-plane program command configured with a plurality of sub-commands, the memory device 100 may perform the multi-plane program operation of simultaneously performing program operations respectively corresponding to the plurality of planes.
[0129] When the corresponding program command is not the multi-plane program command (S1220, No), the memory device 100 may initialize a cache latch of a corresponding plane and may perform the single plane program operation (S1250).”].
2. The memory device of claim 1, wherein the memory device is configured to initialize cache latches of a target plane according to the command [Lee teaches “[0112] FIG. 10 is a diagram illustrating an embodiment of operation of a latch initialization controller 140 shown with the page buffer group 123… [0113] Referring to FIG. 10, the latch initialization controller 140 may control the page buffer group 123 to perform an initialization operation of simultaneously initializing at least two cache latches (among cache latches) in response to a multi-plane program command. In one embodiment, the latch initialization controller 140 may include a target latch determiner 141 and a page buffer controller 143.” “[0126] When the corresponding program command is the multi-program command (S1220, Yes), the memory device 100 may simultaneously initialize cache latches of a plurality of planes (S1230)… [0127]… the memory device 100 may control a target latch to be initialized by transmitting the cache reset signal CRST to the corresponding target latch.” “[0129] When the corresponding program command is not the multi-plane program command (S1220, No), the memory device 100 may initialize a cache latch of a corresponding plane and may perform the single plane program operation (S1250).”].
3. The memory device of claim 2, further comprising a cache latch control logic configured to provide, to the page buffer circuit, a first cache latch initialization signal for initializing the first cache latches and a second cache latch initialization signal for initializing the second cache latches [The rationale in the rejection of claim 2 is herein incorporated. Note Lee teaches latch initialization controller 140 (fig. 10 and related text) which corresponds to the cache latch control logic].
4. The memory device of claim 3, wherein the command comprises different commands for each of the first plane, the second plane, and the target plane [Lee teaches “[0090] The memory device 100 may sequentially receive the first to twelfth sub-commands Sub 1 to Sub 12. The sub-commands may correspond to a plurality of planes. For example, the first sub-command Sub 1, the fifth sub-command Sub 5, and the ninth sub-command Sub 9 may correspond to a first plane, the second sub-command Sub 2, the sixth sub-command Sub 6, and the tenth sub-command Sub 10 may correspond to a second plane, the third sub-command Sub 3, the seventh sub-command Sub 7, and the eleventh sub-command Sub 11 may correspond to a third plane, and the fourth sub-command Sub 4, the eighth sub-command Sub 8, and the twelfth sub-command Sub 12 may correspond to a fourth plane.” “[0125]…the memory device 100 may determine whether the program command received from the memory controller 200 is a multi-plane program command (S1220)… may determine whether the corresponding program command is a multi-plane program command or a single plane program command. For example, as described in FIGS. 7 to 9, when 01h and 80h are included in the program command decoded by the memory device 100, the memory device 100 may identify that the corresponding program command is the multi-plane command for performing the multi-plane program operation.” Where “[0114] The target latch determiner 141 may determine a target latch on which the initialization operation is to be performed (among the cache latches) based on a plurality of sub-commands. For example, the target latch determiner 141 may decode sub-commands received from an external controller and may determine at least two cache latches (among the cache latches in the memory device 100) as the target latches of the initialization operation according to a sub-command.” “[0121] The memory device 100 may simultaneously initialize a plurality of cache latches based on the plurality of sub-commands (S1120). In one embodiment, the cache latch may be a latch which corresponds to each plane and which receives data to be stored in each plane. In one embodiment, the memory device 100 may determine at least two target latches on which initialization is to be performed (among the plurality of cache latches) based on the plurality of sub-commands. For example, the memory device 100 may determine all of the plurality of cache latches as target latches.” “[0129] When the corresponding program command is not the multi-plane program command (S1220, No), the memory device 100 may initialize a cache latch of a corresponding plane and may perform the single plane program operation (S1250).” Thus, different commands, at least when issuing commands which are not the multi-plane command may be provided for different latches in each of the planes, including different commands targeting first plane and a second plane or a target plane].
5. The memory device of claim 3, wherein the command is configured to be one-to-one matched with the first plane, the second plane, and the target plane [The rationale in the rejection of claim 4 is herein incorporated. Note Lee teaches ““[0125]…the memory device 100 may determine whether the program command received from the memory controller 200 is a multi-plane program command (S1220)… may determine whether the corresponding program command is a multi-plane program command or a single plane program command…” thus, commands directed to any of first, second and any target plane are one-to-one matched to the given plane].
6. The memory device of claim 3, wherein command bits of each input/output line are configured to be matched with the first plane, the second plane, and the target plane [The rationale in the rejection of claim 4 is herein incorporated. Lee further teaches “[0093] For example, referring to the first sub-command Sub 1, the memory device 100 may receive commands 7-1 and 7-2 and an address 7-3. For example, the memory device 100 may identify that the first sub-command Sub 1 is a multi-plane command (for performing the multi-plane program operation) based on 01h and 80h and may identify that the data to be input is LSB data (corresponding to the LSB page) based on 01h among the received commands. Also, the memory device 100 may identify which plane among the plurality of planes the data to be input is data to be stored in based on ADDR.” Where CMD, ADDR, DATA are matched to bit lines in each of the accessed planed (figs. 2-3 and related text)].
9. The memory device of claim 3, wherein the cache latch control logic includes: a first page buffer driver configured to generate the first cache latch initialization signal and provide the first cache latch initialization signal to the first cache latches according to the target plane information; and a second page buffer driver configured to generate the second cache latch initialization signal and provide the second cache latch initialization signal to the second cache latches according to the target plane information [Lee teaches [0067] Also, the control logic 130 may include a latch initialization controller 140 which may determine a target latch to perform an initialization operation based on a plurality of sub-commands, and which may control the page buffer group 123 (which includes a plurality of page buffer circuits as shown in fig. 3 and related text) to initialize the determined target latch. Also, the latch initialization controller 140 may control the page buffer group 123 to move data stored in one latch to another latch connected to the same bit line. Other features will be described with reference to FIG. 10… [0070]… the peripheral circuit 120′ may drive the first to fourth memory cell array 110a to 110d under the control of the control logic 130 or the latch initialization controller 140… [0072] The page buffer circuit 1230 may be connected to the memory cell array 110 through a bit line BL and may operate under control of the control logic 130 in a program operation. For example, the page buffer circuit 1230 may perform a cache latch initialization operation or an operation of moving data between latches. Also, the page buffer circuit 1230 may exchange data with the column decoder through a data line DL.”].
10. The memory device of claim 3, further comprising: third to n-th planes; and third to n-th cache latches, wherein the cache latch control logic is configured to initialize the first cache latches, the second cache latches, and the third to n-th cache latches according to the command [Lee teaches a plurality of planes including third and fourth planes fig. 3 and related text; see figs. 2 and 4A and related text].
11. A memory controller for controlling a memory device, the memory device comprising: a memory cell array including a first plane and a second plane; a page buffer circuit including first cache latches configured to store data in the first plane and second cache latches configured to store data in the second plane; and a cache latch control logic configured to provide, to the page buffer circuit, a first cache latch initialization signal for initializing the first cache latches and a second cache latch initialization signal for initializing the second cache latches, wherein the memory controller is configured to provide a command comprising target plane information to the memory device during a program operation, and wherein at least one of the first cache latches and the second cache latches are configured to be selectively initialized according to the target plane information [The rationale in the rejection of claims 1-3 is herein incorporated. Lee further teaches memory controller 200 where “[0043] The memory controller 200 may control the memory device 100 to autonomously perform a program operation, a read operation, or an erase operation… [0044] In accordance with an embodiment, the memory controller 200 may provide a multi-plane program command to the memory device 100…” (fig. 1 and related text)].
12. The memory controller of claim 11, wherein the command is configured to have different commands for each of the first plane and the second plane [The rationale in the rejection of claim 4 is herein incorporated].
13. The memory controller of claim 11, wherein the command is configured to be one-to-one matched with the first plane and the second plane [The rationale int the rejection of claim 5 is herein incorporated].
14. The memory controller of claim 11, wherein command bits of input/output lines are matched with the first plane and the second plane [The rationale in the rejection of claim 6 is herein incorporated].
16. A cache latch initialization method of a memory device connected to a memory controller through input/output lines, the memory device comprising: a memory cell array including first to n-th planes; a page buffer circuit including first to n-th cache latches, first cache latches configured to store data in the first plane, and the n-th cache latches configured to store data in the n-th plane; a cache latch control logic configured to generate first to n-th cache latch initialization signals, the first cache latch initialization signal configured to initialize the first cache latches, the n-th cache latch initialization signal configured to initialize the n-th cache latches, and provide the first to n-th cache latch initialization signals to the page buffer circuit, wherein the cache latch initialization method comprises: receiving target plane information during a program operation; and providing, according to the target plane information, one of the first cache latch initialization signal to the first cache latches or the n-th cache latch initialization signal to the n-th cache latches [The rationale in the rejection of claims 1-3 is herein incorporated. Lee further teaches memory controller 200 where “[0043] The memory controller 200 may control the memory device 100 to autonomously perform a program operation, a read operation, or an erase operation… [0044] In accordance with an embodiment, the memory controller 200 may provide a multi-plane program command to the memory device 100…” (fig. 1 and related text). Note Lee teaches first to fourth planes in fig. 3 and related text].
17. The cache latch initialization method of The cache latch initialization method of wherein the program operation includes: receiving a command including the target plane information from the memory controller; receiving column addresses and row addresses from the memory controller; and receiving data from the memory controller, and wherein the first to n-th cache latch initialization signals are provided during receiving the column addresses and/or the row addresses [Lee teaches “[0048] The peripheral circuit 120 may be configured to perform a program operation, a read operation or an erase operation on a selected area of the memory cell array 110 under the control of the control logic 130. For example, the peripheral circuit 120 may drive the memory cell array 110 under the control of the control logic 130. In one embodiment, peripheral circuit 120 may apply one or more operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under control of the control logic 130… [0049] The peripheral circuit 120 may include, for example, row decoder 121, a voltage generator 122, the page buffer group 123, a column decoder 124, an input/output circuit 125, and a sensing circuit 126… [0050] The row decoder 121 may be connected to the memory cell array 110 through the row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include a pipe select line… [0051] The row decoder 121 may operate under the control of control logic 130 and may receive a row address RADD from the control logic 130. The row decoder 121 may then decode the row address RADD, and may then select at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. Also, the row decoder 121 may select at least one word line of the selected memory block, to apply voltages generated by the voltage generator 122 to the at least one word line WL according the decoded address.” “[0062] The column decoder 124 may communicate data between the input/output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may communicate data with the first to nth page buffers PB1 to PBn through data lines DL, or may communicate data with the input/output circuit 125 through column lines CL… [0063] The input/output circuit 125 may transfer a command CMD and an address ADDR, received from the memory controller 200, to the control logic 130 or may exchange data DATA with the column decoder 124… [0065] The control logic 130 may control the peripheral circuit 120 by outputting the operation signal OPSIG, the row address RADD, the page buffer control signals PBSIGNALS, and the allow bit VRYBIT in response to the command CMD and the address ADDR. In accordance with an embodiment, the control logic 130 may control the page buffer group 123 to initialize a cache latch in the page buffer group 123 using the page buffer control signals PBSIGNALS. The cache latch may be, for example, a latch which receives data to be stored in a memory cell.”].
18. The cache latch initialization method of claim 17, wherein the command is configured to have a different command for each of the first to n-th planes [The rationale in the rejection of claim 4 is herein incorporated].
19. The cache latch initialization method of claim 17, wherein the command is configured to be one-to-one matched with each of the first to n-th planes [The rationale int the rejection of claim 5 is herein incorporated].
20. The cache latch initialization method of claim 17, wherein command bits of input/output lines are matched with each of the first to n-th planes [The rationale in the rejection of claim 6 is herein incorporated].
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). Lim (US 9032108) teaches “A semiconductor device includes a memory block including memory cells coupled to bit lines, read/write circuits each including cache latch suitable for temporarily storing data to be stored in the memory cells, wherein the read/write circuits are divided into a plurality of groups and perform a program operation to store the data in the memory cells coupled to the bit lines, and an initialization control unit suitable for initializing the cache latches of the read/write circuits of a group corresponding to the address before the data is input to the cache latches, when a program command and an address are input.” (Abstract).
Jung et al. (US 10,459,667) teaches “The control logic 1160 may include a target latch manager 1165. The target latch manager 1165 receives a target latch command TLC during a multi-bit program operation. In example embodiments, the target latch manager 1165 may initialize a target latch with reference to a program command or a column address and a row address without receiving a separate target latch command. The target latch manager 1165 may classify a type of data as a combination of the column address and the row address to initialize a target latch corresponding to the type of data. The target latch manager 1165 may be implemented with a logic circuit or implemented in software.” (col. 4, lines 56-67). 1
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-14 and 16-20 have received a first action on the merits and are subject of a first action non-final.
a(2) ALLOWABLE SUBJECT MATTER
The subject matter of claim 7 would be objected to (if the 35 USC 112 rejections of claim 6 above are overcome) as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims, and if the 35 USC 112 rejections of claim 6 above are overcome.
7. The memory device of The memory device of wherein the first cache latches are configured to be initialized based on a command bit of a first input/output line being 1, and wherein the second cache latches are configured to be initialized based on a command bit of a second input/output line being 1.
Claim 8 would be objected to if the 35 USC 112 rejections of claim 6 above are overcome, based on its dependence on objected claim 7.
8. The memory device of claim 6, wherein the first cache latches and the second cache latches are both configured to be initialized based on command bits of first and second input/output lines all being 1.
Per the instant office action, claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
15. The memory controller of The memory controller of wherein the first cache latches are configured to be initialized based on a command bit of a first input/output line being 1, and wherein the second cache latches configured to be are initialized based on a command bit of a second input/output line being 1.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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July 17, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
Prosecution Insights