DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
Examiner suggests amending “A display substrate, comprising a plurality…” to read –A display substrate, comprising: a plurality..— in order to place the claim in better form.
Appropriate correction is required.
A series of singular dependent claims is permissible in which a dependent claim refers to a preceding claim which, in turn, refers to another preceding claim.
A claim which depends from a dependent claim should not be separated by any claim which does not also depend from said dependent claim. It should be kept in mind that a dependent claim may refer to any preceding independent claim. In general, applicant's sequence will not be changed. See MPEP § 608.01(n).
For example, claim 7 depends on claim 6, claim 8 depends on claim 5, and claims 9-11 again depend on claim 6.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 5-6, and 14-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12417740. Please see the chart below for claim correspondence.
19/290280
USPN12417740
1
14
2
14 (11)
3
--
4
--
5
14 (1)
6
14 (1)
7
--
8
--
9
--
10
--
11
--
12
--
13
--
14
14 (11)
15
16
16
17
Although the claims at issue are not identical, they are not patentably distinct from each other because:
The claims as shown above all recite similar features. It would have been obvious to one of ordinary skill in the art to use the claimed features of the reference application/patent to arrive at the instant claims, yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement.
Please see an example of claim language correspondence below.
19/290280
USPN12417740
1. A display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, wherein at least one of the circuit units comprises a pixel drive circuit,
1. A display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel drive circuit, the pixel drive circuit at least comprises a compensation transistor, a drive transistor, a data writing transistor, a first node, a second node, a first storage capacitor and a second storage capacitor, the pixel drive circuit is connected with a first scan signal line, a second scan signal line, a first power supply line and a data signal line, respectively; a gate electrode of the drive transistor is connected with the second node, a first electrode of the drive transistor is connected with the first node, and a second electrode of the drive transistor is connected with a second electrode of the compensation transistor; a gate electrode of the data writing transistor is connected with the first scan signal line, a first electrode of the data writing transistor is connected with the data signal line, and a second electrode of the data writing transistor is connected with the first node; a gate electrode of the compensation transistor is connected with the second scan signal line, and a first electrode of the compensation transistor is connected with the second node; a first end of the first storage capacitor is connected with the second node, and a second end of the first storage capacitor is connected with the first power supply line; a first end of the second storage capacitor is connected with the first node, and a second end of the second storage capacitor is connected with the first power supply line;
on a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially on a base substrate;
wherein on a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer which are disposed sequentially on a base substrate; the first end of the first storage capacitor comprises a first electrode plate, the second end of the first storage capacitor comprises a second electrode plate, the first electrode plate is disposed in the first conductive layer, and the second electrode plate is disposed in the second conductive layer; the first end of the second storage capacitor at least comprises a third electrode plate, the second end of the second storage capacitor comprises a fourth electrode plate, the third electrode plate is disposed in the semiconductor layer, and the fourth electrode plate is disposed in the second conductive layer.
the second conductive layer comprises a first initial signal line and a second initial signal line extending along a first direction,
13. The display substrate according to claim 11, wherein on a plane perpendicular to the display substrate, the display substrate further comprises a fourth conductive layer disposed subsequently on a side of the third conductive layer away from the base substrate; the first initial signal line and the second initial signal line are disposed in the second conductive layer, and the first connection line and the second connection line are disposed in the fourth conductive layer.
the third conductive layer comprises a first connection line and a second connection line extending along a second direction; and
14. The display substrate according to claim 13, wherein the third conductive layer in at least one circuit unit further comprises a first initial electrode, the first connection line is connected with the first initial electrode through a via, and the first initial electrode is connected with the first initial signal line through a via; or the third conductive layer in at least one circuit unit further comprises a second initial electrode, the second connection line is connected with the second initial electrode through a via, and the second initial electrode is connected with the second initial signal line through a via.
the first connection line is electrically connected to the first initial signal line through a first via, the second connection line is electrically connected to the second initial signal line through a second via,
14. The display substrate according to claim 13, wherein the third conductive layer in at least one circuit unit further comprises a first initial electrode, the first connection line is connected with the first initial electrode through a via, and the first initial electrode is connected with the first initial signal line through a via; or the third conductive layer in at least one circuit unit further comprises a second initial electrode, the second connection line is connected with the second initial electrode through a via, and the second initial electrode is connected with the second initial signal line through a via.
and the first direction intersects with the second direction.
11. The display substrate according to claim 1, wherein the pixel drive circuit is further connected with a first initial signal line and a second initial signal line respectively, shapes of the first initial signal line and the second initial signal line are line shapes extending along a first direction; the first initial signal line is connected with a first connection line extending along a second direction to form a mesh structure for transmitting a first initial signal, the second initial signal line is connected with a second connection line extending along the second direction to form a mesh structure for transmitting a second initial signal, and the first direction intersects with the second direction.
The rest of the claims listed above correspond in a similar manner as discussed above.
Allowable Subject Matter
Claims 3, 4, and 7-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM R GIESY whose telephone number is (571)272-7555. The examiner can normally be reached Mon-Fri 8-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 5712727603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM R. GIESY/ Primary Examiner, Art Unit 2622
Prosecution Insights