DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/4/25 and 5/12/2026 were considered by the examiner.
Drawings
The drawings received on 8/05/2025 were accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dennis et al. [2010/0318747], Applicant Cited Art.
Claim 1, Dennis et al. discloses a method [par. 0006, 0011, 0014], comprising: starting, based on a state of a cache line that is in a memory and when the cache line changes from a non-modified state to a modified state, a timer of the cache line [par. 0019-0022; invalid, valid, dirty states; transitioning states; update main memory when timer expires]; and writing the cache line back to a next-level memory when the timer expires [par. 0011, 0014, 0021, 0023; when timer expires, the new AMO result is propagated to main memory].
Claim 2, Dennis et al. discloses the method of claim 1, wherein after starting the, the method further comprises writing the cache line back to the next- level memory when the timer does not expire, and when a write-back event occurs [par. 0011, 0014].
Claim 3, Dennis et al. discloses the method of claim 2, wherein the write-back event comprises an eviction operation on the cache line [par. 0011, 0014, 0022, 0024].
Claim 4. Dennis et al. discloses the method of claim 1, wherein after writing the cache line, the method further comprises [par. 0023]: changing the state from the modified state to the non-modified state [par. 0023; dirty is the modified state and valid is the non modified state]; and restarting the timer [par.0021-0022; subsequent modifications re-trigger and reset the write timer].
Claim 5, Dennis et al. discloses the method of claim 1, wherein, starting the timer comprises: performing a modification operation on the cache line, to change the state from the non-modified state to the modified state; and starting, in response to the modification operation, the timer [par. 0022].
Claim 6, Dennis et al. discloses the method of claim 1, wherein an entry of the cache line comprises a tag, data, and an attribute, wherein the tag comprises a physical address of the data, and wherein the attribute comprises a count value of the timer [par. 0020-0022].
Claim 7, Dennis et al. discloses the method of claim 1, further comprising storing in the memory a timing unit of the timer, wherein the timing unit indicates a periodicity of updating a count value of the timer [par. 0021].
Claims 8-19 are rejected using the same rationale as claims 1-7.
Claim 20, Dennis et al. discloses the apparatus of claim 8, wherein the apparatus is a chip [see par. 0003, 0018].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Steely, JR et al. [US 2002/0103976]; Adaptive Dirty Block Purging, See par. 0080.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133
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