DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/05/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claims 1, 10, 19 and 29, recite the limitation “the secure memory”. There is insufficient antecedent basis for the limitation in the claims.
The claims also recite the limitation “outside the first address range for secure memory”. The limitation is open to interpretation. The claims initially recite “reserving a first address range…for non-secure memory”. Thus, “outside the first address range for the secure memory” is indefinite because the first address range is reserved for non-secure memory.
The claims further recite the limitation “the first address range is less than the second address range”. The term “less than” is relative and ambiguous. Does it mean the size of the first range or something else?
The claims also recite the limitation “reserving a first memory address range within a first address range” and then further recites “reserving a second memory address range within a second address range and outside the first address range”. The limitations are open to interpretation because the initially recites reserving within first address range and then reserving within second range outside, so it is unclear whether the recited “first address range” and “the second address range” are part of the one single address range or they are different address ranges.
The claims depending upon the rejected claims fail to cure the deficiencies of the rejected claims and therefore rejected under same rationales as applied to the rejected claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-30 of U.S. Patent No. 12,393,525. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of patent ‘525 anticipate claims of current application. (see following comparison of the claims).
App. No. 19/291,197
U.S. Patent No. 12,393,525
1. A method for accessing secure memory ranges comprising: reserving a first memory address range within a first address range for non-secure memory;
reserving a second memory address range within a second address range and outside the first address range for secure memory, wherein the first address range is less than the second address range; receiving, by a first kernel, a first command from a first application for accessing the secure memory;
preparing, by the first kernel, a first memory access command based on the first command;
transmitting, by the first kernel, the first memory access command to a graphics processing unit (GPU); and
accessing, by the GPU, the secure memory based on the first memory access command.
2. The method of claim 1, further comprising: generating a first page table for the first application, wherein the first page table maps a first virtual address within the second address range to a first physical address in the secure memory; and generating a second page table for a second application, wherein the second page table maps the first virtual address to a second physical address in the secure memory.
3. The method of claim 2, further comprising, in response to receiving the first command, setting, by a GPU driver, a base address value at a memory management unit (MMU) to a first address value corresponding to a location of the first page table, wherein transmitting the first memory access command to the GPU further comprises transmitting the first memory access command to the GPU after setting the base address value to the first address value.
4. The method of claim 3, further comprising determining, by the MMU, the first physical address corresponding to the first virtual address based on the first page table, wherein accessing the secure memory based on the first memory access command further comprises accessing the secure memory using the first physical address.
5. The method of claim 3, further comprising: receiving, by the first kernel, a second command from the second application for accessing the secure memory; in response to receiving the second command, setting, by the GPU driver, the base address value at the MMU to a second address value corresponding to a location of the second page table; preparing, by the first kernel, a second memory access command based on the second command; and transmitting, by the first kernel, the second memory access command to the GPU after setting the base address value to the second address value.
6. The method of claim 5, further comprising, in response to receiving the second command, determining whether execution of the first command is completed, wherein setting the base address value at the MMU to the second address value further comprises setting the base address value at the MMU to the second address value after determining that execution of the first command is completed.
7. The method of claim 1, wherein: the first memory address range comprises a first range of virtual addresses corresponding to non-secure memory resources; and the second memory address range comprises a second range of virtual addresses corresponding to secure memory resources.
8. The method of claim 1, wherein preparing the first memory access command further comprises associating, by the first kernel, a second virtual address to the first command, wherein the first memory access command comprises the second virtual address and the first command.
9. The method of claim 1, wherein the reserving the first memory address range and the reserving the second memory address range is performed by a GPU driver of the first kernel.
1. A method for accessing secure memory ranges comprising: reserving a first memory address range within a 32-bit address range for non-secure memory;
reserving a second memory address range within a 64-bit address range and outside the 32-bit address range for secure memory;
receiving, by a 64-bit kernel, a first command from a 32-bit application for accessing the secure memory;
preparing, by the 64-bit kernel, a 64-bit memory access command based on the first command;
transmitting, by the 64-bit kernel, the 64-bit memory access command to a graphics processing unit (GPU); and accessing, by the GPU, the secure memory based on the 64-bit memory access command.
2. The method of claim 1, further comprising: generating a first page table for the 32-bit application, wherein the first page table maps a first 64-bit virtual address within the 64-bit address range to a first physical address in the secure memory; and generating a second page table for a second 32-bit application, wherein the second page table maps the first 64-bit virtual address to a second physical address in the secure memory.
3. The method of claim 2, further comprising, in response to receiving the first command, setting, by a GPU driver, a base address value at a memory management unit (MMU) to a first address value corresponding to a location of the first page table, wherein transmitting the 64-bit memory access command to the GPU further comprises transmitting the 64-bit memory access command to the GPU after setting the base address value to the first address value.
4. The method of claim 3, further comprising determining, by the MMU, the first physical address corresponding to the first 64-bit virtual address based on the first page table, wherein accessing the secure memory based on the 64-bit memory access command further comprises accessing the secure memory using the first physical address.
5. The method of claim 3, further comprising: receiving, by the 64-bit kernel, a second command from the second 32-bit application for accessing the secure memory; in response to receiving the second command, setting, by the GPU driver, the base address value at the MMU to a second address value corresponding to a location of the second page table; preparing, by the 64-bit kernel, a second 64-bit memory access command based on the second command; and transmitting, by the 64-bit kernel, the second 64-bit memory access command to the GPU after setting the base address value to the second address value.
6. The method of claim 5, further comprising, in response to receiving the second command, determining whether execution of the first command is completed, wherein setting the base address value at the MMU to the second address value further comprises setting the base address value at the MMU to the second address value after determining that execution of the first command is completed.
7. The method of claim 1, wherein: the first memory address range comprises a first range of virtual addresses corresponding to non-secure memory resources; and the second memory address range comprises a second range of virtual addresses corresponding to secure memory resources.
8. The method of claim 1, wherein preparing the 64-bit memory access command further comprises associating, by the 64-bit kernel, a 64-bit virtual address to the first command, wherein the 64-bit memory access command comprises the 64-bit virtual address and the first command.
9. The method of claim 1, wherein the reserving the first memory address range and the reserving the second memory address range is performed by a GPU driver of the 64-bit kernel.
As can be seen from above comparison of the claims of the current application with the claims of patent, the 32-bit address range of the patent claims is equivalent to the first address range and the 64-bit address range is equivalent to the second address range. Thus, claims of the patent anticipate claims of the current application. Claims 10-30 of the current application are respectively mapped against the claims 10-30 of the patent claims.
Allowable Subject Matter
Claims 1-30 will be allowed over prior arts of record.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements (35 USC 112(b) rejection of the claims and double patenting rejection) or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
As per independent claims 1, 10, 19 and 29, prior arts of record Bond et al. (US 2002/0052727), Bond et al. (US 2019/0294537) (Bond-1), Patel et al. (US 2014/0365742) teach a computer system running 32-bit applications (first address range) and 64-bit applications (second address range) (Bond: pars. [0013], [0017], [0024] – [0030], [0068] – [0070]; Bond-1: fig. 2; Patel: figs. 6 and 7 and related description), however prior arts of record fail to teach or suggest reserving a first memory address range within first address range for non-secure memory; reserving a second memory address range within a second address range and outside the first address range for secure memory; receiving, by a first kernel, a first command from a first application for accessing the secure memory; preparing, by the first kernel, a first memory access command based on the first command; transmitting, by the first kernel, the first memory access command to a graphics processing unit (GPU); and accessing, by the GPU, the secure memory based on the first memory access command.
Conclusion
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
Prosecution Insights