DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on application KR10-2025-0030758 filed in Korea on March 10, 2025.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 6, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
MPEP 2111.04(II) provides that “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.”.
Claim 14 recites “wherein, in response to a determination that a number of read commands which are externally received during a predetermined first time period and which request to read the first data unit among the plurality of data units is equal to or greater than a first threshold number of read commands, the determining whether to cache includes determining to cache the first data unit in the cache.”
The act of determining to cache the first data unit in the cache is explicitly premised on the condition of a determination that a number of read commands… is equal to or greater than first threshold number of read commands. This determination is not recited as required within the broadest reasonable interpretation of the scope of claim 14, and therefore the determining to cache the first data unit is also not required within the broadest reasonable interpretation of the scope of claim 14.
Claim 15 recites “evicting, in response to a determination that a number of times the first data unit cached in the cache is accessed during a predetermined second time period is less than a threshold number of accesses, the first data unit cached in the cache from the cache.”
The act of evicting the first data unit is conditioned on multiple items: the first data unit is cached in the cache, and also that a number of times that the data unit is accessed during a second time period is less than a threshold number of accesses. Claim 15 does not recite any step that modifies the determination of claim 14 that the determining to cache the first data unit in the cache step is required, and therefore, the condition of first data unit being in the cache is not required within the broadest reasonable interpretation of the claim. Further, there is no step recited that explicitly requires the determination regarding the second time period within the broadest reasonable interpretation of the claim, and therefore this condition is also not required. As a result, claim 15’s step of evicting the data is not required within the broadest reasonable interpretation of the claim scope.
Claim 16 recites “evicting the first data unit cached in the cache from the cache, in response to a determination that the number of read commands for reading the first data unit among M number of read commands externally received is less than a second threshold number of read commands, where M is a natural number.”
The act of evicting the first data unit is conditioned on multiple items: the first data unit is cached in the cache, and also that the number of read commands is less than a second threshold number of read commands. Claim 16 does not recite any step that modifies the determination of claim 14 that the determining to cache the first data unit in the cache step is required, and therefore, the condition of first data unit being in the cache is not required within the broadest reasonable interpretation of the claim. Further, there is no step recited that explicitly requires the determination regarding the second threshold number of read commands within the broadest reasonable interpretation of the claim, and therefore this condition is also not required. As a result, claim 16’s step of evicting the data is not required within the broadest reasonable interpretation of the claim scope.
Examiner notes that if applicant seeks to require these steps within the broadest reasonable interpretation of the claim, the claims may be amended to either remove the condition that leads to these limitations being considered as contingent limitations or to explicitly require the conditions identified in the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 and 14-16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 14 recite “that request to read the first data unit among the plurality of data units”, but this is the first recitation of “the first data unit” in either the instant claims or their parent claims. For the purpose of examination, it is assumed these instead recite “a first data unit”.
Claims 7, 8, 15, and 16 are rejected due to dependence on claims 6 and 14.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 14-16 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claims 14-16 recite limitations that have been identified as contingent limitations and upon analysis, the contingent limitations are not required within the broadest reasonable interpretation of the claims. As these are the only limitations in claims 14-16, then claims 14-16 effectively recite no limitations that further limit the subject matter of the claims from which they depend, meriting this rejection.
Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that the dependent claims complies with the statutory requirements. Examiner notes that an amendment to the claims to address the claim interpretation of the contingent limitations as discussed above would be sufficient to address this rejection, as requiring the claim limitations will clearly introduce limitations that further limit the claims from which the instant claims depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6, 9-11, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2024/0192860) in view of Lee et al. (US 2026/0065048) and Shilomi et al. (US 2025/0156164).
Regarding claim 1, Zhang teaches a storage device (Fig. 3, KVSSD) comprising:
a memory configured to store a plurality of data units (Fig. 3, SCM storing KV cache, see [0041,0042]); and
a controller (Fig. 3, SSD controller) configured to determine the plurality of data units (Fig. 9, provides processing a KV operation including write/update/read operations, which necessarily requires a determination of relevant KV data, see also [0076], and determine whether to cache each of the plurality of data units in a cache (Fig. 9, steps S912-S920 determine whether to cache KV data into the KV cache in the SCM based on a read count).
Zhang fails to teach each data unit including at least one of parameters of an artificial intelligence model and where the controller is configured to externally receive structure information on the artificial intelligence model, and as a result where the determining of the plurality of data units is based on the structure information.
While Zhang does disclose how data operations can be AI related, see [0108], this is not enough detail to teach where the data units store parameters of an artificial intelligence model.
Lee’s disclosure relates to the operation of an artificial intelligence model, and as such comprises analogous art in the same field of endeavor of artificial intelligence models.
As part of this disclosure, Lee depicts an AI model with multiple layers in Fig. 3, which processes prompt tokens and inserts into a pretrained LLM. As part of this, Lee provides that “The embeddings 312 generated from the tokenized version of the input prompt 305 may be accompanied by a number of forecasted token embeddings 314 associated with future predictions of inputs into the generative artificial intelligence model 320. These forecasted token embeddings 314, for example, may be embeddings associated with predicted tokens corresponding to words or parts of words predicted to be part of an output that is subsequently appended to the input prompt for future generation of additional portions of the response to the input prompt in subsequent inferencing rounds using the generative artificial intelligence model 320. In some aspects, the forecasted token embeddings 314 input into the generative artificial intelligence model 320 may be accompanied by a forecasted prefix 316 prepended to an internal cache 318 (labeled as a KV (key-value) cache in FIG. 3, though it should be recognized that the internal cache may be any appropriate cache that can be used by the generative artificial intelligence model 320 to store and access previously processed data for subsequent inferencing) used by the generative artificial intelligence model 320 for generating a response to the input prompt. As illustrated, the forecasted prefix 316 may be a prefix for the internal cache 318 (e.g., a key-value cache or other data cache) used by transformer layers of a large language model, large multimodal model, or other transformer-based generative artificial intelligence model to condition the generation of attention outputs which are used in sampling tokens to serve as a response to the input prompt,” [0050].
An obvious combination can be identified: combining Lee’s technique of utilizing KV caches for storing AI model data into Zhang’s storage device. This reads upon where the data unit includes parameters of an artificial intelligence model, as Lee discloses how the KV cache can store data and prefixes utilized by the AI model.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Lee’s disclosure of how the KV caches are utilized in AI model processing into Zhang’s storage device operating with KV caches. Both elements are available as prior art. In addition, as Zhang already discloses utilizing the storage device for performing AI operations generally as well as the provision of a KV cache, Lee’s further detail concerning how a KV cache can be utilized in performance of AI operations provides a predictable result: where Zhang’s storage device and KV cache can operate AI models, including how the AI model stores data within the KV cache.
The combination of Zhang and Lee still fails to teach the reception of structural information of the artificial intelligence data, and then determining the data units based on the structural information.
Shilomi’s disclosure relates to providing AI model templates, and as such comprises analogous art in the same field of endeavor of artificial intelligence models, and more specifically related to structural information about the AI models.
As part of this disclosure, Shilomi general disclosure relates to operating AI models, where there is a base AI model and a new AI model, where the new AI model can have different structural parameters such as a number of layers, parameters, caches, which can be compared to the base model, see [0020]. Further, Shilomi identifies that “For example, the compiler may change, in the code of the base AI model, the value of a feed forward dimension, change a KV cache size, specify an activation function to use, specify whether the use a gated activation, change the number of decoder layers, change the number of heads, and so forth, using the values in the new structural parameters. In this manner, values in the code for the base AI model are replaced with values in the structural parameters,” [0036].
An obvious modification can be identified: incorporating Shilomi’s disclosure of being able to depict/receive different structural parameters, and further where this can affect aspects of the AI model, including the size of the KV cache size, into the combination of Zhang and Lee. Shilomi’s description of receiving and compiling new AI models based on the received structural parameters reads on the reception of the structure information of the AI model, and as Zhang and Lee utilize the KV cache in order to store data for the AI model operation, see the discussion above, and Zhang discusses how the size of the KV cache can affect read performance, see [0042], then incorporating the detail that the structural parameters can affect the KV cache reads upon the determination of the data units based on the structure information.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Shilomi’s disclosure of modifying AI models based on structural parameters, including modifying KV cache sizes, into Zhang and Lee, as this allows for a greater control and degree of design flexibility to a user implementing different AI models in Zhang’s hardware, including how memory is allocated/utilized for the AI model operations.
Regarding claim 2, the combination of Zhang, Lee, and Shilomi teaches the storage device according to claim 1, wherein the structure information includes at least one of:
a number of processors that access the artificial intelligence model in parallel;
a number of parameters of the artificial intelligence model (“As non-limiting examples, the new structural parameters 115 can describe… the number of heads, a maximum distance associated with performing attention,… etc.,” Shilomi [0021]);
a size of each parameter of the artificial intelligence model (“As non-limiting examples, the new structural parameters 115 can describe a feed forward dimension, … a maximum distance associated with performing attention, the number of buckets associated with self-attention, etc.,” Shilomi [0021]); and
layer information of the artificial intelligence model (“As non-limiting examples, the new structural parameters 115 can describe … the number of decoder layers, … etc.,“ Shilomi [0021] ).
Regarding claim 3, the combination of Zhang, Lee, and Shilomi teaches the storage device according to claim 1, wherein a first data unit among the plurality of data units includes parameters that are included in a first layer among layers of the artificial intelligence model (as discussed in the claim 1 rationale, Lee [0050] provides that data stored in the KV cache can include embeddings associated with the embedding layer, prefixes input into the LLM, and processed data associated with the LLM) .
Regarding claim 6, the combination of Zhang, Lee, and Shilomi teaches the storage device according to claim 1, wherein, when a number of read commands that are externally received during a predetermined first time period and that request to read the first data unit among the plurality of data units is equal to or greater than a first threshold number of read commands, the controller is configured to determine to cache the first data unit in the cache (“ In addition, to reduce occupancy of the SCM and overhead of maintaining the cache, threshold values kvReadThres and kvUpdateThres are set in embodiments of the disclosure to cache only the data whose read count is not lower than the kvReadThres and whose update count is not higher than the kvUpdateThres,” [0042] teaching that only data with a read count higher than the read threshold is cached, see also [0079]).
Claims 9 is directed to a method claim that recites method steps identical to the functional limitations of the storage device of claim 1, and as such can be rejected according to the same rationale of claim 1.
Claims 10 and 11 are rejected according to the same rationale of claims 2 and 3.
Claims 14-16 are rejected under 35 U.S.C. 112(d) as failing to further limit the subject matter of claim 9 due to the contingent limitations. As such, claims 14-16 as currently recited can also be rejected according to the rationale of claim 9.
Claim 14 can also be rejected according to the same rationale of claim 6.
Claims 4, 5, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Lee and Shilomi and further in view of Bert (US 2026/0227910)
Regarding claim 4, the combination of Zhang, Lee, and Shilomi teaches the storage device according to claim 3, but fails to teach wherein the first data unit corresponds to one continuous logical address area.
Bert’s disclosure is related to caching data in a storage system and as such comprises analogous art in the same field of endeavor of caching data.
As part of this disclosure, Bert discloses that “the read command (e.g., 171) can request the retrieval of the data from a contiguous segment of logical block addresses. For example, the segment can be specified in the read command (e.g., 171) via the starting logical block address (e.g., 134) and a size of the segment (or an ending logical block address),” [0182] and “Multiple contiguous units of memory cells (e.g., 123) having consecutive memory addresses (e.g., 124) in the memory space 121 can be used to store respective portions of the data 126 retrieved from the logical block address 134,” [0095].
An obvious combination can be identified: combining Bert’s disclosure of commands specifying data based on continuous segments of logical block addresses and storing the data retrieved in contiguous units of memory cells into Zhang’s system with caching data in the KV cache. Such a combination reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine Bert’s continuous LBA-based caching with Zhang’s system. Both elements are known in the art, and as Bert provides further detail on how Zhang’s system can access/cache data, then one of ordinary skill in the art would recognize such a combination to lead to a predictable result, with Zhang’s system operating via accessing continuous logical address areas for read commands.
Regarding claim 5, the combination of Zhang, Lee, Shilomi, and Bert teaches the storage device according to claim 4, wherein the first data unit is stored in one continuous physical address area of the memory (as part of the disclosure in the claim 4 rationale, Bert identifies how data retrieved from the logical addresses can be stored in a contiguous area of memory cells, i.e. a continuous physical address area, reading on the limitation of the claim).
Claims 12 and 13 are rejected according to the same rationale of claims 4 and 5.
Claims 7, 8, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Lee and Shilomi and further in view of Tamilarasan et al. (US 2023/0325324).
Regarding claim 7, the combination of Zhang, Lee, and Shilomi teaches the storage device according to claim 6, wherein, when a number of times the first data unit cached in the cache is accessed during a predetermined second time period is less than a threshold number of accesses, the controller is configured to evict the first data unit cached in the cache from the cache.
While Zhang discloses when to cache data into the KV cache, see Fig. 9, Zhang provides a general eviction based on LRU policy instead of a comparison with a read count as claimed.
Tamilarasan’s disclosure relates to caching systems, and as such comprises analogous art in the same field of endeavor of caching.
As part of this disclosure, Tamilarasan discloses how a caching policy can promote/demote data based on a frequency of cache hits, where “The cache hit metric can be based on, for example, a frequency or rate of cache hits, a cache hit ratio determined with respect to a defined time period or average, and the like. For example, in at least one embodiment, the deduplicated data cache policy can classify a cached data block as belonging to one of the multiple tiers where there may be three such tiers denoted as low, medium and high, where low denotes the lowest tier of cache hit frequency or ratio, medium denotes the second highest tier of cache hit frequency or ratio, and high denotes the highest tier of cache hit frequency or ratio. When a data block is initially promoted to the deduplicated data cache, the data block can be classified as belonging to the low tier. Over time, based on the number of times the cached data block is accessed (e.g., as a result of a cache hit with respect to the deduplicated data cache), the data block can be further promoted within the deduplicated data cache to a higher ranked tier, such as promoted from the low tier to the medium or high tier. For example, a first cache hit threshold can be defined as 10 indicating that once the cached data block is accessed 10 times, such as during a defined time period, the cached data block can be further promoted to the medium tier. While in the medium tier, if the cached data block is accessed at least 50 times during a defined time period, the data block can be further promoted from the medium to the high tier. Generally, an embodiment can define different promotion and also demotion tier thresholds regarding cache hit frequency, rate or ratio used for promoting and demoting cached data between the different tiers and also for eviction or demotion from the deduplicated data cache,” [0196].
An obvious modification can be identified: incorporating Tamilarasan’s disclosure of a time-based cache hit metric to compare with a threshold to determine when to cache/promote data blocks and also similar thresholds to determine when to demote and evict the data blocks from the cache. Such a modification reads upon the limitation of the claim, as Tamilarasan tracks the cache hit metric threshold over a period of time.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Tamilarasan’s disclosure of promotion/demotion thresholds based on a cache hit metric into Zhang’s disclosure, as Tamilarasan’s use of the cache hit metric to determine when to demote/evict increases the likelihood that a data object evicted is not as likely to be accessed soon, rather than just selecting a least recently used item, which may still be relatively hot compared to other data items.
Regarding claim 8, the combination of Zhang, Lee, and Shilomi teaches the storage device according to claim 6, but fails to teach wherein, when a number of read commands for reading the first data unit among M number of read commands externally received is less than a second threshold number of read commands, the controller is configured to evict the first data unit cached in the cache from the cache, where M is a natural number.
While Zhang discloses when to cache data into the KV cache, see Fig. 9, Zhang provides a general eviction based on LRU policy instead of a comparison with a read count as claimed.
Tamilarasan’s disclosure relates to caching systems, and as such comprises analogous art in the same field of endeavor of caching.
As part of this disclosure, Tamilarasan discloses how a caching policy can promote/demote data based on a frequency of cache hits, where “The cache hit metric can be based on, for example, a frequency or rate of cache hits, a cache hit ratio determined with respect to a defined time period or average, and the like. For example, in at least one embodiment, the deduplicated data cache policy can classify a cached data block as belonging to one of the multiple tiers where there may be three such tiers denoted as low, medium and high, where low denotes the lowest tier of cache hit frequency or ratio, medium denotes the second highest tier of cache hit frequency or ratio, and high denotes the highest tier of cache hit frequency or ratio. When a data block is initially promoted to the deduplicated data cache, the data block can be classified as belonging to the low tier. Over time, based on the number of times the cached data block is accessed (e.g., as a result of a cache hit with respect to the deduplicated data cache), the data block can be further promoted within the deduplicated data cache to a higher ranked tier, such as promoted from the low tier to the medium or high tier. For example, a first cache hit threshold can be defined as 10 indicating that once the cached data block is accessed 10 times, such as during a defined time period, the cached data block can be further promoted to the medium tier. While in the medium tier, if the cached data block is accessed at least 50 times during a defined time period, the data block can be further promoted from the medium to the high tier. Generally, an embodiment can define different promotion and also demotion tier thresholds regarding cache hit frequency, rate or ratio used for promoting and demoting cached data between the different tiers and also for eviction or demotion from the deduplicated data cache,” [0196].
An obvious modification can be identified: incorporating Tamilarasan’s disclosure of a time based cache hit metric to compare with a threshold to determine when to cache/promote data blocks and also similar thresholds to determine when to demote and evict the data blocks from the cache. Such a modification reads upon the limitation of the claim, as Tamilarasan provides example number thresholds of when to promote and also discloses similar design of thresholds for determining when to demote/evict data.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Tamilarasan’s disclosure of promotion/demotion thresholds based on a cache hit metric into Zhang’s disclosure, as Tamilarasan’s use of the cache hit metric to determine when to demote/evict increases the likelihood that a data object evicted is not as likely to be accessed soon, rather than just selecting a least recently used item, which may still be relatively hot compared to other data items.
Examiner notes that while the subject matter is currently not required in the broadest reasonable interpretation of the claims, the subject matter of claims 15 and 16 can be rejected according to the same rationale of claims 7 and 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Radhakrishnan et al. (US 12,282,663), Wu et al. (US 2017/0075812), Gupta et al. (US 2021/0263862), disclose utilizing read counts for determine how to move data between tiers/caches,
Pudipeddi et al. (US 2021/0019152), Lu et al. (US 2022/0155970), Petersen et al. (US 2023/0153938), Fenzl et al. (US 2024/0020169) disclose caching AI model parameters,
Jain et al. (US 2024/0007414) discloses managing AI model parameters, including how caches are utilized based on different models,
Ramanujan et al. (US 2024/0419493) discloses managing KV cache for AI workloads,
Raichelgauz (US 2025/0389541) discloses providing data/structures between different AI models.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON D HO whose telephone number is (469)295-9093. The examiner can normally be reached Mon-Fri 8:00-4:00 CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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