DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 are pending
Claims 11, 15, 18 and 20 are objected to
Claims 17 and 19 are rejected under 35 USC § 102
Claims 1-10, 12-14, 16 are rejected under 35 USC § 103
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/06/2025 and 04/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8-10, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over SHARON; ERAN et al. (US 20170255403 A1)[Sharon] in view of SHARON; ERAN et al. (US 20210191651 A1)[Sharon1]
Regarding claim 1 Sharon discloses:
A storage device comprising:
a memory device comprising a memory cell array, the memory cell array comprising a plurality of memory cells (Sharon: [0042]: teaches a memory device 103 of the data storage device 102 including one or more memory dies. The memory device 103 includes a memory 104. The memory 104 is a non-volatile memory having a 3D memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells); and
a memory controller configured to, in response to a read command from a host device [indicating first data and comprising a tag indicating target data is to be temperature managed,] obtain a read offset from a read offset table based on first temperature information corresponding to the first data, change an initial read voltage to a read voltage based on the read offset, and read the first data from the memory device using the read voltage (Sharon: [0046-0047], Fig. 1: teaches a controller 120 being coupled to the memory device 103 and is configured to receive data and instructions from the access device 180 and to send data to the access device 180 and is configured to send data and commands to the memory 104 and receive data from the memory 104. Sharon: [0081], Fig. 6: teaches data that is received at the controller 120 to be written to the memory device 103 is associated with time data and temperature data. For example, first received data 650 is associated with first time data 652 and first temperature data 654. The first time data 652 corresponds to a chronological time. The first temperature data 654 received from a temperature sensor of the memory device 103, such as the temperature sensor 112 of FIG. 1. The time and temperature group manager 602 compare the first time data 652 to the current group time threshold 606 and compare the first temperature data 654 to the current group temperature threshold 608.
Every read/write command is accompanied by an address to read from or write to, and the address is similar to the tag. Controller receiving temperature data from the host during write and storing it based on address is similar to the tag (similar to write address) indicating that the written data (target data for future read) is temperature managed.
Sharon: [0031]: teaches rather than storing memory access parameters (e.g., read voltages) corresponding to specific temperatures or temperature ranges, offset values is used. When programming data at a given temperature, there is a set of read parameters that is “optimum” for reading the data at the given temperature. This temperature is recorded at the system level, and the “optimum” read condition is calculated or determined (e.g., by means of CVD tracking or BES). When the data is read, the read temperature is measured. If the temperature difference between the write temperature and the read temperature is larger than a threshold, then a read offset is applied to the original read condition (e.g., as an adjustment from the “optimum” read parameter) so that the resulting read parameters enable a more accurate read of the data based on the temperature difference. If the temperature difference is relatively small, then the data may be accessed with the original reading condition without any offset compensation).
Sharon teaches adjusting read voltage based on temperature shift however Sharon did not explicitly disclose the tag indicating target data to be temperature managed in the read command.
Sharon1 discloses:
a memory controller configured to, in response to a read command from a host device indicating first data and comprising a tag indicating target data is to be temperature managed, obtain a read offset from a read offset table based on first temperature information corresponding to the first data, change an initial read voltage to a read voltage based on the read offset, and read the first data from the memory device using the read voltage (Sharon1: [0137]: teaches metadata module 1010 records metadata for regions of a non-volatile memory array 200 (e.g., bytes, pages, blocks, or the like) at write time, and retrieve metadata at read time. The metadata module 1010 records time and temperature metadata for a region of memory cells at write time. Sharon1: [0139]: teaches current conditions module 1014 determine current conditions for values that are recorded by the metadata module 1010, such as a current time, and/or a current temperature. At read time, the read mode module 902 in some embodiments may select a read mode based on metadata from the metadata module 1010 and/or based on current conditions from the current conditions module 1014. Sharon1: [0140]: teaches the read mode module 902 selecting a read mode for reading data from a region of a memory array 200 based on metadata recorded by the metadata module 1010 at write time for the region. The read mode module 902 selecting between a hard bit read mode, a time-based soft bit read mode, and/or a bias-based soft bit read mode based on metadata such as a time/temperature tag indicating a time and temperature at write time for a region. Sharon1: [0141]: teaches the read mode module 902 selecting a read mode for reading data from a region of a memory array 200 based on a comparison of the current time and temperature, obtained from the current conditions module 1014, time and temperature metadata recorded at write time for the region, obtained from the metadata module 1010.
So, Sharon1's system saves/records time and temperature metadata for a region of memory cells at write time. Any read command uses a read address (can be called tag) to read data from. Sharon1's system uses the tag to determine the location to be read from and determines appropriate read mode to read data which includes getting appropriate voltage adjustment with correct voltage offset due to temperature change.
Sharon1's using read mode module during read based on memory location to be read from using the read address/tag is similar to indicator indicating that the target data is to be temperature managed).
Both Sharon and Sharon1 represent works within the same field of endeavor, namely information processing devices focusing data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Sharon in view of Sharon1 as it represents a combination of known prior art elements according to known methods (accurate data reading method of Sharon using read mode for reading data from a region of a memory array 200 based on a comparison of the current time and temperature as used in Sharon1's system) to yield a more accurate and robust memory access system (see also Sharon1 [0137-0141])
Regarding claim 3 Sharon/Sharon1 discloses:
The storage device of claim 1, wherein the tag further indicates a temperature range comprising a temperature of the storage device before starting a read operation for the first data (Sharon1: [0137]: teaches metadata module 1010 records metadata for regions of a non-volatile memory array 200 (e.g., bytes, pages, blocks, or the like) at write time, and retrieve metadata at read time. The metadata module 1010 records time and temperature metadata for a region of memory cells at write time. Sharon1: [0139]: teaches current conditions module 1014 determine current conditions for values that are recorded by the metadata module 1010, such as a current time, and/or a current temperature. At read time, the read mode module 902 in some embodiments may select a read mode based on metadata from the metadata module 1010 and/or based on current conditions from the current conditions module 1014. Sharon1: [0140]: teaches the read mode module 902 select a read mode for reading data from a region of a memory array 200 based on metadata recorded by the metadata module 1010 at write time for the region. The read mode module 902 selecting between a hard bit read mode, a time-based soft bit read mode, and/or a bias-based soft bit read mode based on metadata such as a time/temperature tag indicating a time and temperature at write time for a region, a program/erase cycle count, or the like. Sharon1: [0141]: teaches the read mode module 902 selecting a read mode for reading data from a region of a memory array 200 based on a comparison of the current time and temperature, obtained from the current conditions module 1014, to time and temperature metadata recorded at write time for the region, obtained from the metadata module 1010.
So, Sharon1's system saves/records time and temperature metadata for a region of memory cells at write time. All read command uses a read address (can be called tag) to read data from. Sharon1's system uses the tag to determine the location to be read from and determines appropriate read mode to read data which includes getting appropriate voltage adjustment with correct voltage offset due to temperature change.
Sharon1's using read mode module during read based on memory location to be read from using the read address/tag is similar to indicator indicating that the target data is to be temperature managed. So, the metadata for regions of a non-volatile memory related to the address/tag and identifying the temperature range comprising the temperature of the storage device based on the related metadata is similar to indicating a temperature range by the tag ).
Regarding claim 4 Sharon/Sharon1 discloses:
The storage device of claim 1, wherein the first temperature information comprises:
a first temperature of the storage device before starting a previous write operation for a memory region corresponding to an address range comprising an address of the first data (Sharon: [0081], Fig. 6: teaches data that is received at the controller 120 to be written to the memory device 103 is associated with time data and temperature data. For example, first received data 650 is associated with first time data 652 and first temperature data 654.
Writing data involves a location to be written and thus temperature data associated with a write command indicates temperature data associated with the location (address range) to be written by the write command);
and a second temperature of the storage device before starting a read operation for the first data (Sharon: [0031]: teaches - when the data is read, the read temperature is measured. If the temperature difference between the write temperature and the read temperature is larger than a threshold, then a read offset is applied to the original read condition (e.g., as an adjustment from the “optimum” read parameter) so that the resulting read parameters enable a more accurate read of the data based on the temperature difference.
The temperature measured before executing read operation is the second temperature).
Regarding claim 5 Sharon/Sharon1 discloses:
The storage device of claim 4, wherein the read offset is identified based on a first temperature range comprising the first temperature, a second temperature range comprising the second temperature, and a difference between the first temperature range and the second temperature range (Sharon: [0031]: teaches - when the data is read, the read temperature is measured. If the temperature difference between the write temperature and the read temperature is larger than a threshold, then a read offset is applied to the original read condition (e.g., as an adjustment from the “optimum” read parameter) so that the resulting read parameters enable a more accurate read of the data based on the temperature difference).
Regarding claim 6 Sharon/Sharon1 discloses:
The storage device of claim 4, wherein the read offset table comprises a plurality of read offsets mapped to a plurality of first temperature ranges and a plurality of second temperature ranges (Sharon: [0067], FIG. 3: teaches an offset table that is used in the data storage device 102. An adjusted read voltage is generated by or based on a sum of a default value of the read voltage 301 and an offset retrieved from an offset table 302. The offset table 302 includes multiple columns, each column corresponding to a respective read temperature range (second temperature ranges). The offset table 302 also includes a number of rows, each row corresponding to a respective write temperature range (first temperature ranges).).
Regarding claim 8 Sharon/Sharon1 discloses:
The storage device of claim 4, wherein the read offset table comprises a plurality of first read offsets mapped to some of a plurality of first temperature ranges and some of a plurality of second temperature ranges (Sharon: [0067], FIG. 3: teaches an offset table that is used in the data storage device 102. An adjusted read voltage is generated by or based on a sum of a default value of the read voltage 301 and an offset retrieved from an offset table 302. The offset table 302 includes multiple columns, each column corresponding to a respective read temperature range (second temperature ranges). The offset table 302 also includes a number of rows, each row corresponding to a respective write temperature range (first temperature ranges)).
Regarding claim 9 Sharon/Sharon1 discloses:
The storage device of claim 8, wherein some of the plurality of first temperature ranges and some of the plurality of second temperature ranges are determined based on an operation environment of the storage device (Sharon: [0059-0066], FIG. 2: teaches an example 200 of performing temperature range adjustment. For example, a first graph 202 indicates a distribution of historical temperature measures 230 associated with storage of data or retrieval of data from the memory device 103 of FIG. 1. Three or more temperature ranges may be determined, such as a first temperature range 220, a second temperature range 222, and a third temperature range 224. In response to the range adjustment 250 determining that the distribution of newer historical temperature measures 232 includes a portion of measurements, the range adjuster 138 may adjust one or more of the thresholds 210-214. Because temperature effects on data storage and retrieval is primarily based on a temperature difference between write temperatures and read temperatures, by adjusting the temperature ranges 220-224 based on a recent history of historical temperature measures, a proportion of data write and/or data reads occurring in the abnormal temperature range(s) is reduced, resulting in a higher performance and lower error rates as compared to operation using the unadjusted temperature ranges 220-224.).
Regarding claim 10 Sharon/Sharon1 discloses:
The storage device of claim 8, wherein the memory controller is further configured to update the read offset table by mapping a plurality of second read offsets to a remainder of the plurality of first temperature ranges and a remainder of the plurality of second temperature ranges (Sharon: [0067-0070] FIG. 3: teaches a sum of a default value of the read voltage 301 and an offset retrieved from an offset table 302. The offset table 302 includes multiple columns, each column corresponding to a respective read temperature range. The offset table 302 also includes a number of rows, each row corresponding to a respective write temperature range. Range 0 from a temperature of −25 degrees (e.g., degrees Celsius) to a temperature of 0 degrees. Range 1 corresponds to a temperature in the range from one degree to 25 degrees. Range 2 corresponds to a temperature between 26 and 50 degrees. Range 3 corresponds to a temperature from 51 degrees to 75 degrees. Range 4 corresponds to a temperature from 76 degrees to 100 degrees. five temperature ranges, a total of four negative offset values and four positive offset values may be used. Thus, a reduced amount of data is used to adjust for differences in read temperature ranges using a relatively small amount of offset data as compared to including a distinct offset value for each temperature difference).
Regarding claim 12 Sharon/Sharon1 discloses:
The storage device of claim 1, wherein the plurality of memory cells comprise:
first memory cells configured to be operated as one of a multiple level cell (MLC), a triple level cell (TLC), and a quadruple level cell (QLC) to store the target data (Sharon: [0044]: teaches each storage element of the memory 104 is programmable to a state (e.g., a threshold voltage in a flash configuration) that indicates one or more values. Each block of the memory 104 includes one or more word lines. Each word line includes one or more pages, such as one or more physical pages. A word line is configurable to operate as a multi-level-cell (MLC) word line, or as a tri-level-cell (TLC) word line);
and second memory cells configured to be operated as single level cells (SLC) to store general data comprising driving data (Sharon: [0044]: teaches each storage element of the memory 104 is programmable to a state (e.g., a threshold voltage in a flash configuration) that indicates one or more values. Each block of the memory 104 includes one or more word lines. Each word line includes one or more pages, such as one or more physical pages. A word line is configurable to operate as a single-level-cell (SLC) word line).
Regarding claim 13 Sharon/Sharon1 discloses:
The storage device of claim 1, wherein the memory controller is further configured to manage a write management table based on the tag and an address, and write second data to the memory device in response to a write command that indicates the second data and comprises the tag (Sharon: [0081], Fig. 6: teaches data that is received at the controller 120 to be written to the memory device 103 is associated with time data and temperature data. For example, first received data 650 is associated with first time data 652 and first temperature data 654. The first time data 652 corresponds to a chronological time. The first temperature data 654 received from a temperature sensor of the memory device 103, such as the temperature sensor 112 of FIG. 1. The time and temperature group manager 602 compare the first time data 652 to the current group time threshold 606 and compare the first temperature data 654 to the current group temperature threshold 608. In response to determining that the first time data 652 does not exceed the current group time threshold 606 and that the first temperature data 654 does not exceed the current group temperature threshold 608, the time and group temperature manager 602 associates the first data 650 with the current group N, and provides the first access memory parameter 630 to the memory device 103 for storage of the first data 650.
Sharon teaches each write data being accompanied by ‘time data’ and ‘temperature data’. If it is a second write command then it will include second data, second time data and second temperature data and the address to where data will be written is similar to the tag).
Claims 2 are rejected under 35 U.S.C. 103 as being unpatentable over SHARON; ERAN et al. (US 20170255403 A1)[Sharon] in view of SHARON; ERAN et al. (US 20210191651 A1)[Sharon1] further in view of Niwa, Akimasa et al. (US 20030142570 A1)[Niwa]
Regarding claim 2 Sharon/Sharon1 teaches all the limitations of claim 1. However, Sharon/Sharon1 did not explicitly disclose tag comprising bits at positions designated through a memory standard among bits included in the read command.
Niwa discloses:
The storage device of claim 1, wherein the tag comprises bits at positions designated through a memory standard among bits included in the read command (Niwa: [0032], FIG. 1B: teaches an instruction bit train includes a first partial bit train P1 of m-bit expressing command such as a write instruction and a read instruction, a second partial bit train P2 of n-bit expressing address for designating storing position of the memory 6, and a third partial bit train P3 of p-bit expressing data to be inputted or outputted from or to the memory 6.
The address bits (of the read command) are similar to the tag bits).
Both Sharon/Sharon1 and Niwa represent works within the same field of endeavor, namely information processing devices focusing data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Sharon/Sharon1 in view of Niwa as it represents a combination of known prior art elements according to known methods (accurate data reading method of Sharon/Sharon1 using read command with command, address and data bits as used in Niwa's system) to yield a more accurate and robust memory access system (see also Niwa [0032])
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over SHARON; ERAN et al. (US 20170255403 A1)[Sharon] in view of SHARON; ERAN et al. (US 20210191651 A1)[Sharon1] further in view of Chien; Jia-Fan et al. (US 20230071724 A1)[Chien]
Regarding claim 14 Sharon/Sharon1 teaches all the limitations of claim 13. However, Sharon/Sharon1 did not explicitly disclose comparing a second write temperature with the first write temperature to the same region and taking action based on the comparison result.
Chien discloses:
The storage device of claim 13, wherein the memory controller is further configured to obtain, from the write management table, a first temperature of the storage device before starting a previous write operation for a memory region corresponding to an address range comprising the address, and manage the write management table based on a comparison of a temperature of the storage device before starting a write operation for the second data with the first temperature (Chien: [0072-0073], FIG. 9: teaches near a second time point, the memory management circuit 51 receives a write command 901 from the host system 11. The write command 901 instructs to store data 902 (also referred to as second data) to the physical unit 71. It is assumed that the first write temperature status and the second write temperature status meet the first condition - the temperature difference value (between first and second temperature) falls within a specific value range. In response to the first temperature status and the second temperature status meeting the first condition, the memory management circuit 51 reset the temperature status corresponding to the physical unit 71 in the table information 700 to the parameter value “000”.).
Both Sharon/Sharon1 and Chien represent works within the same field of endeavor, namely information processing devices focusing data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Sharon/Sharon1 in view of Chien as it represents a combination of known prior art elements according to known methods (accurate data reading method of Sharon/Sharon1 checking during second write the temperature value of the first write to same memory region and manage the write management table based on the write as used in Chien's system) to yield a more accurate and robust memory access system (see also Chien [0072-0073])
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over SHARON; ERAN et al. (US 20170255403 A1)[Sharon] in view of SHARON; ERAN et al. (US 20210191651 A1)[Sharon1] further in view of Park; Sehwan et al. (US 11556415 B2)[Park]
Regarding claim 7 Sharon/Sharon1 teaches all the limitations of claim 6. However, Sharon/Sharon1 did not explicitly disclose controller monitoring operation at a specific temperature that is not covered by offset table and add a new entry in the read offset table based on the monitoring result.
Park discloses:
The storage device of claim 6, wherein the memory controller is further configured to monitor operation of the storage device while operating in a specific temperature environment that is not covered by the read offset table to obtain a monitoring result, and add a new read offset corresponding to the specific temperature environment to the read offset table based on the monitoring result (Jin: claim 1, col4/ln61-col5/ln2, col12/ln51-col12/ln60: teaches A memory controller comprising: a buffer memory configured to store a table in which a static offset voltage for a read operation is written, and to store a machine learning model that receives cell count information corresponding to a threshold voltage distribution of memory cells included in the at least one memory device and generates a dynamic offset voltage for the read operation; an error correction circuit; and a processor configured to, when the error correction circuit fails to correct an error in read data obtained from the at least one memory device, instruct the at least one memory device to perform an optimal read operation of adjusting an operating condition of the read operation and obtaining read data, wherein, when the error correction circuit successfully corrects an error in read data obtained by the optimal read operation, the processor inputs the cell count information, received from the at least one memory device as a result of the optimal read operation, to the machine learning model to obtain the dynamic offset voltage and updates the table using the dynamic offset voltage.).
Both Sharon/Sharon1 and Park represent works within the same field of endeavor, namely information processing devices focusing data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Sharon/Sharon1 in view of Park as it represents a combination of known prior art elements according to known methods (accurate data reading method of Sharon/Sharon1 updating offset table with new entry when correct offset value is missing for some specific condition as used in Park's system) to yield a more accurate and robust memory access system (see also Park claim 1, col4/ln61-col5/ln2, col12/ln51-col12/ln60).
Regarding claim 16 Sharon/Sharon1 teaches all the limitations of claim 1. However, Sharon/Sharon1 did not explicitly disclose controller performing read recovery based on failure to read the first data, and update the read offset table based on a read recovery result.
Park discloses:
The storage device of claim 1, wherein the memory controller is further configured to perform read recovery based on failure to read the first data, and update the read offset table based on a read recovery result (Jin: claim 1, col4/ln61-col5/ln2, col12/ln51-col12/ln60: teaches A memory controller comprising: a buffer memory configured to store a table in which a static offset voltage for a read operation is written, and to store a machine learning model that receives cell count information corresponding to a threshold voltage distribution of memory cells included in the at least one memory device and generates a dynamic offset voltage for the read operation; an error correction circuit; and a processor configured to, when the error correction circuit fails to correct an error in read data obtained from the at least one memory device, instruct the at least one memory device to perform an optimal read operation of adjusting an operating condition of the read operation and obtaining read data, wherein, when the error correction circuit successfully corrects an error in read data obtained by the optimal read operation, the processor inputs the cell count information, received from the at least one memory device as a result of the optimal read operation, to the machine learning model to obtain the dynamic offset voltage and updates the table using the dynamic offset voltage).
Both Sharon/Sharon1 and Park represent works within the same field of endeavor, namely information processing devices focusing data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Sharon/Sharon1 in view of Park as it represents a combination of known prior art elements according to known methods (accurate data reading method of Sharon/Sharon1 updating offset table with new entry when correct offset value is missing for some specific condition as used in Park's system) to yield a more accurate and robust memory access system (see also Park claim 1, col4/ln61-col5/ln2, col12/ln51-col12/ln60).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHARON; ERAN et al. (US 20170255403 A1)[Sharon]
Regarding Claim 17 Sharon discloses:
An electronic device comprising:
a host device configured to process data for controlling vehicle driving (Sharon:[0035], FIG. 1: teaches a system 100 that includes a data storage device 102 which includes a controller 120 and an access device 180. The controller 120 and the access device 180 are coupled via a connection (e.g., a communication path), such as a bus or a wireless connection. The controller 120 includes a first interface 124 e.g., an access device or host interface) that enables communication via the communication path between the controller 102 and the access device 180. The combination of controller 120 and access device 180 is the host device.);
system memory allocated to the host device and configured to load a read offset table (Sharon:[0035], FIG. 1: teaches the controller 120 includes a temperature-based adjuster 122 that is configured to perform compensation based on temperature differences between writing data to a memory 104 and reading the data from the memory 104. The temperature-based adjuster 122 is also configured to perform compensation based on a programming temperature (e.g., a temperature of the memory 104 that is measured just before, during, or after data is written into the memory 104) being outside of a “normal” temperature range.); and
a storage device configured to perform a memory operation based on a command received from the host device (Sharon:[0035, 0040], FIG. 1: teaches a data storage device 102 including or corresponding to a solid state drive (SSD) communicating via the memory interface to read data from and write data to the memory device 103 of the data storage device 102. ),
wherein the host device is further configured to obtain a read offset from the read offset table based on first temperature information corresponding to first data to be temperature managed, and transmit a read command, the read offset, and a first address for the first data to the storage device (Sharon:[0054], FIG. 1: teaches [0054] a trim adjuster 136 configured to adjust one or more parameters used during writing data to or reading data from the memory 104. The trim adjuster 136 is configured to retrieve one or more offset values from the table 128 based on the difference between a temperature that the data is written to the memory 104 and a temperature at which the data is to be read from the memory 104. When the controller 120 receives the request from the access device 180 to read the data 106, the controller 120 retrieves the write temperature 108 from the memory 104 and further instruct the temperature sensor 112 to perform a measurement operation and to provide the read temperature 162 to the controller 120. The trim adjuster 136 is configured to use a difference between the read temperature 162 and the write temperature 108 to determine an index into the table 128. For example, a temperature difference (illustrated as ΔT1) corresponds to a first change in read voltages 152 (ΔVR1). Different amounts of temperature difference corresponds to different amounts of read voltage offset values that is retrieved from the table 128. The trim adjuster 136 is configured to adjust a default value of one or more trim parameters based on offset values retrieved from table 128 and to provide the adjusted values to the memory device 103 for use during data retrieval from memory 104.).
Regarding claim 19 Sharon discloses:
A storage device comprising:
a memory device comprising a memory cell array, the memory cell array comprising a plurality of memory cells (Sharon:[0035, 0040], FIG. 1: teaches a data storage device 102 including or corresponding to a solid state drive (SSD) communicating via the memory interface to read data from and write data to the memory device 103 of the data storage device 102.); and
a memory controller configured to control the memory device to perform, in conjunction with a host device, one of a write operation and a read operation for data to be temperature managed, based on temperature information corresponding to the data (Sharon: [0046-0047], Fig. 1: teaches a controller 120 being coupled to the memory device 103 and is configured to receive data and instructions from the access device 180 (host) and to send data to the access device 180 (host) and is configured to send data and commands to the memory 104 and receive data from the memory 104. Sharon: [0081], Fig. 6: teaches data that is received at the controller 120 to be written to the memory device 103 is associated with time data and temperature data. For example, first received data 650 is associated with first time data 652 and first temperature data 654. The first time data 652 corresponds to a chronological time. The first temperature data 654 received from a temperature sensor of the memory device 103, such as the temperature sensor 112 of FIG. 1. The time and temperature group manager 602 compare the first time data 652 to the current group time threshold 606 and compare the first temperature data 654 to the current group temperature threshold 608. Sharon: [0031]: teaches rather than storing memory access parameters (e.g., read voltages) corresponding to specific temperatures or temperature ranges, offset values is used. When programming data at a given temperature, there is a set of read parameters that is “optimum” for reading the data at the given temperature. This temperature is recorded at the system level, and the “optimum” read condition is calculated or determined (e.g., by means of CVD tracking or BES). When the data is read, the read temperature can be measured. If the temperature difference between the write temperature and the read temperature is larger than a threshold, then a read offset is applied to the original read condition (e.g., as an adjustment from the “optimum” read parameter) so that the resulting read parameters enable a more accurate read of the data based on the temperature difference. If the temperature difference is relatively small, then the data may be accessed with the original reading condition without any offset compensation).
Allowable Subject Matter
Claims 11, 15, 18 and 20 are being objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 recites, ‘The storage device of claim 8, wherein the memory controller is further configured to transmit a thermal management request to the host device to control the second temperature of the storage device to be changed to be within the plurality of second temperature ranges’.
Prior art Achtenberg; Stella et al. (US 20180374548 A1)[Achtenberg] [0099]: teaches a predictive indicator that may be sent by a host and used by a non-volatile memory system to select a code rate for user data is an indicator of one or more expected environmental conditions such as expected temperature range during a data retention period. In general, data that is stored in non-volatile memory degrades faster at when the read and write temperatures are very different leading to more data retention errors when data is stored in a non-volatile memory that is exposed to temperatures that are different to the temperature when written. Thus, the number of bad bits (i.e. bit error rate, or “BER”) in stored data tends to increase faster at higher or lower temperature than the write temperature. Where a host gives an indicator as to what temperature range may be expected for a non-volatile memory during a period when data is stored, this may help to select an appropriate code rate. Furthermore, data that is stored (programmed and verified) at a first temperature and is subsequently read at a second temperature may have a higher BER than data that is programmed and read at the same temperature. Thus, temperature changes is significant and temperature data is provided with respect to the temperature when data was stored (i.e. as relative temperature rather than absolute temperature). A value such as delta T may be provided by a host for individual components within a memory system such as for an individual non-volatile memory unit. In some memory systems, a memory system is embedded in a host and is at substantially the same temperature as host components so that expected host temperature is used as expected non-volatile memory temperature.
Achtenberg teaches host providing second temperature.
However, Achtenberg does not teach controller further configuring to transmit a thermal management request to the host device to control the second temperature of the storage device to be changed to be within the plurality of second temperature ranges.
Prior art Sumiyoshi, Tohru et al. (US 20030093586 A1)[Sumiyoshi]: [0008]: teaches the enclosure manager 14 responding to a request (SES command) from the host system 2 to send internal temperature of the disk enclosure 3, and other control and management information to the host system 2 through the controller of the HDD 6 and the FC-AL 5, and control the disk enclosure 3 properly through internal loop control and other control for the disk enclosure 3.
Sumiyoshi teaches control and management information being sent (transmitted) to the host system 2 through the controller of the HDD 6.
However, in Sumiyoshi host requested/initiated to send internal temperature of the disk enclosure 3. Sumiyoshi does not teach controller further configuring to transmit a thermal management request to the host device to control the second temperature of the storage device to be changed to be within the plurality of second temperature ranges.
No known prior arts taken alone or in combination teaches, controller further configuring to transmit a thermal management request to the host device to control the second temperature of the storage device to be changed to be within the plurality of second temperature ranges.
Claim 15 states, ‘The storage device of claim 13, wherein the memory controller is further configured to transmit a thermal management request to the host device to control a temperature of the storage device, and to start a write operation for the second data based on a current temperature being covered by the read offset table’.
Prior art Achtenberg; Stella et al. (US 20180374548 A1)[Achtenberg] [0099]: teaches a predictive indicator that may be sent by a host and used by a non-volatile memory system to select a code rate for user data is an indicator of one or more expected environmental conditions such as expected temperature range during a data retention period. In general, data that is stored in non-volatile memory degrades faster at when the read and write temperatures are very different leading to more data retention errors when data is stored in a non-volatile memory that is exposed to temperatures that are different to the temperature when written. Thus, the number of bad bits (i.e. bit error rate, or “BER”) in stored data tends to increase faster at higher or lower temperature than the write temperature. Where a host gives an indicator as to what temperature range may be expected for a non-volatile memory during a period when data is stored, this may help to select an appropriate code rate. Furthermore, data that is stored (programmed and verified) at a first temperature and is subsequently read at a second temperature may have a higher BER than data that is programmed and read at the same temperature. Thus, temperature changes is significant and temperature data is provided with respect to the temperature when data was stored (i.e. as relative temperature rather than absolute temperature). A value such as delta T may be provided by a host for individual components within a memory system such as for an individual non-volatile memory unit. In some memory systems, a memory system is embedded in a host and is at substantially the same temperature as host components so that expected host temperature is used as expected non-volatile memory temperature.
Achtenberg teaches host providing second temperature while issuing a second write without
However, Achtenberg does not teach controller further configuring to transmit a thermal management request to the host device to control the second temperature of the storage device and start a second write operation for second data based on a current temperature being covered by the read offset table.
Prior art Sumiyoshi, Tohru et al. (US 20030093586 A1)[Sumiyoshi]: [0008]: teaches the enclosure manager 14 responding to a request (SES command) from the host system 2 to send internal temperature of the disk enclosure 3, and other control and management information to the host system 2 through the controller of the HDD 6 and the FC-AL 5, and control the disk enclosure 3 properly through internal loop control and other control for the disk enclosure 3.
Sumiyoshi teaches control and management information being sent (transmitted) to the host system 2 through the controller of the HDD 6.
However, in Sumiyoshi host requested/initiated to send internal temperature of the disk enclosure 3. Sumiyoshi does not teach controller further configuring to transmit a thermal management request to the host device to control the second temperature of the storage device to be changed to be within the plurality of second temperature ranges.
No known prior arts taken alone or in combination teaches, controller further configuring to transmit a thermal management request to the host device to control the second temperature of the storage device and start a second write operation for second data based on a current temperature being covered by the read offset table. Prior arts teach the normal flow of operation i.e. issue write operation along with temperature info for the second write and memory/storage controller handles the rest without controller sending/transmitting request to the host and host acting based on the request.
Claim 18 states, ‘The electronic device of claim 17, wherein the host device is further configured to identify that the first data is to be temperature managed based on a file header of data corresponding to the first data’.
Prior art SHARON; ERAN et al. (US 20170255403 A1)[Sharon] [0035, 0042-0047] teaches host’s read/write being temperature managed as shared in claim 1, claim 17 and claim 19 above..
Similarly, Prior art SHARON; ERAN et al. (US 20210191651 A1)[Sharon1] [0137-0141] also teaches host’s read/write being temperature managed as shared in claim 1.
However, Sharon/Sharon1 did not disclose that the host device being configured to identify that the first data is temperature managed based on a file header of data corresponding to the first data.
No known prior art taken alone or in combination teaches the host device being configured to identify that the first data is temperature managed based on a file header of data corresponding to the first data.
Claim 20 states, ‘The storage device of claim 19, wherein the memory controller is further configured to identify that the data is to be temperature managed based on specific bits of a command received from the host device’.
Prior art SHARON; ERAN et al. (US 20170255403 A1)[Sharon] [0035, 0042-0047] teaches host’s read/write being temperature managed as shared in claim 1, claim 17 and claim 19 above..
Similarly, Prior art SHARON; ERAN et al. (US 20210191651 A1)[Sharon1] [0137-0141] also teaches host’s read/write being temperature managed as shared in claim 1.
However, Sharon/Sharon1 did not disclose that the host device being configured to identify that the data is temperature managed based on specific bits of a command received from the host device.
No known prior art taken alone or in combination teaches the host device being configured to identify that the data is temperature managed based on specific bits of a command received from the host device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is recorded in pe2e_search_note.pdf and is attached as OA.APPENDIX.
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/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138
