DETAILED ACTION
Claims 1-20 are examined and pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-6. 8-13 and 15-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-8, 10-15, 17-20 of U.S. Patent No.12,417,278 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because all the claimed limitations recited in the present application are transparently found in the Patent 12,417,278 with obvious wording variations. A comparison of the claims are shown below:
Pending Application 19/292276
Patent 12,417,278
1. A system comprising: a memory; a processing device, communicably coupled to the memory, the processing device to perform operations comprising: determining an identifier of a current execution context associated with a memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, associating the memory region with the current execution context; and clearing at least a part of the memory region.
8. A method, comprising: determining, by a processing device, an identifier of a current execution context associated with a memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, associating the memory region with the current execution context; and clearing at least a part of the memory region.
15. A non-transitory machine-readable storage medium storing instructions which, when executed, cause a processing device to perform operations comprising: determining an identifier of a current execution context associated with a memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, associating the memory region with the current execution context; and clearing at least a part of the memory region.
1. A system comprising: a memory; a processing device, communicably coupled to the memory, the processing device to perform operations comprising: receiving a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.
8. A method, comprising: receiving, by a processing device, a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.
15. A non-transitory machine-readable storage medium storing instructions which, when executed, cause a processing device to perform operations comprising: receiving a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.
2. The system of claim 1, wherein the memory region is represented by one of: a cache line, a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
9. The method of claim 8, wherein the memory region is represented by one of: a cache line, a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
16. The non-transitory machine-readable storage medium of claim 15, wherein the memory region is represented by one of: a cache line, a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
3. The system of claim 1, wherein the memory region is represented by one of: a cache line, a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
10. The method of claim 8, wherein the memory region is represented by one of: a cache line, a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
17. The non-transitory machine-readable storage medium of claim 15, wherein the memory region is represented by one of: a cache line, a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
3. The system of claim 1, wherein the current execution context is one of a thread or a process.
10. The method of claim 8, wherein the current execution context is one of a thread or a process.
17. The non-transitory machine-readable storage medium of claim 15, wherein the current execution context is one of a thread or a process.
4. The system of claim 1, wherein the current execution context is one of a thread or a process.
11. The method of claim 8, wherein the current execution context is one of a thread or a process.
18. The non-transitory machine-readable storage medium of claim 15, wherein the current execution context is one of a thread or a process.
4. The system of claim 1, wherein the current execution context is one of: a virtual machine or a container.
11. The method of claim 8, wherein the current execution context is one of: a virtual machine or a container.
18. The non-transitory machine-readable storage medium of claim 15, wherein the current execution context is one of: a virtual machine or a container.
5. The system of claim 1, wherein the current execution context is one of: a virtual machine or a container.
12. The method of claim 8, wherein the current execution context is one of: a virtual machine or a container.
19. The non-transitory machine-readable storage medium of claim 15, wherein the current execution context is one of: a virtual machine or a container.
5. The system of claim 1, wherein the current execution context is a trusted execution environment.
12. The method of claim 8, wherein the current execution context is a trusted execution environment.
19. The non-transitory machine-readable storage medium of claim 15, wherein the current execution context is a trusted execution environment.
6. The system of claim 1, wherein the current execution context is a trusted execution environment.
13. The method of claim 8, wherein the current execution context is a trusted execution environment.
20. The non-transitory machine-readable storage medium of claim 15, wherein the current execution context is a trusted execution environment.
6. The system of claim 1, wherein the processing device is one of: a central processing unit (CPU), a network interface controller (NIC), a data processing unit DPU, or a graphic processing unit (GPU).
13. The method of claim 8, wherein the processing device is one of: a central processing unit (CPU), a network interface controller (NIC), a data processing unit DPU, or a graphic processing unit (GPU).
7. The system of claim 1, wherein the processing device is one of: a central processing unit (CPU), a network interface controller (NIC), a data processing unit DPU, or a graphic processing unit (GPU).
14. The method of claim 8, wherein the processing device is one of: a central processing unit (CPU), a network interface controller (NIC), a data processing unit DPU, or a graphic processing unit (GPU).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Durham et al. (2020/0057664, hereinafter “Durham”) in view of Tsirikin et al. (U.S. 2023/0418643 A1, hereinafter “Tsirikin”).
As to claims 1, 8, and 15, Durham discloses a system comprising: a memory;
a processing device, communicably coupled to the memory, the processing device to perform operations comprising:
determining an identifier of a current execution context associated with a memory region (Figure 2 and para.[0092]; discloses VM1 can be one of the virtual machines in the system can be the current ) ;
determining an identifier of a previous execution context specified by metadata associated with the memory region (Figure 2 and para. [0092]; discloses VM2 will be another virtual machine in the system can be used at any time);
responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, associating the memory region with the current execution context (Figure 2 and para. [0098]; discloses processor switches between VMs and their respective key domains(memory regions) KD1 and KD2 using a switchKD instruction in response to a command issued by the memory manager. The result of switching from one key domain to another (e.g., from key domain KD2 250.sub.2 to KD1 250.sub.1) is that control over a particular physical memory alias is passed to a VM (230.sub.1) that is authorized to access the current key domain KD1 250.sub.1).
However, Durham does not explicitly disclose the system wherein clearing at least a part of the memory region.
In an analogous art, Tsirkin discloses the system wherein clearing at least a part of the memory region. (para. [0048]; discloses hypervisor decides whether to free the memory page by releasing or relinquishing a memory may involve instructing a virtual machine to execute an operation to free memory page)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Durham by incorporating a function to clear memory page when needed as taught by Tsirkin in order to provide a more efficient manner to reallocate storage units for the virtual machines.
As to claim 2, Durham-Tsirkin discloses the system of claim 1, wherein the memory region is represented by one of: a cache line (Durham, para., [0090]) , a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
As to claim 3, Durham-Tsirkin discloses the system of claim 1, wherein the current execution context is one of a thread or a process (Durham, para. [0199]; discloses virtual memory systems manage and allocate memory various processes running within the system).
As to claim 4, Durham-Tsirkin discloses the system of claim 1, wherein the current execution context is one of: a virtual machine or a container (Durham, para. [0065).
As to claim 5, Durham-Tsirkin discloses the system of claim 1, wherein the current execution context is a trusted execution environment (para. [0298]; discloses processor implementing a TEE).
As to claim 6, Durham-Tsirkin discloses the system of claim 1, wherein the processing device is one of: a central processing unit (CPU), a network interface controller (NIC), a data processing unit DPU, or a graphic processing unit (GPU) (Durham, para. [0113]; discloses the processor includes CPU).
As to claim 7, Durham-Tsirkin discloses the system of claim 1, wherein determining the identifier of the current execution context associated with the memory region is performed responsive to reassigning the memory region from the previous execution context to the current execution context (Durham, para. [0089]; discloses the memory manager can access an integrity check value table to determine whether the correct key domain key was used to access the data. If the wrong key domain key was used to decrypt the data, the resulting plaintext will be corrupted and will not match a corresponding integrity check value in the integrity check value table.) .
As to claim 9, Durham-Tsirkin discloses the method of claim 8, wherein the memory region is represented by one of: a cache line (Durham, para., [0090]), a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
As to claim 10, Durham-Tsirkin discloses the method of claim 8, wherein the current execution context is one of a thread or a process (Durham, para. [0199]; discloses virtual memory systems manage and allocate memory various processes running within the system).
As to claim 11, Durham-Tsirkin discloses the method of claim 8, wherein the current execution context is one of: a virtual machine or a container (Durham, para. [0065).
As to claim 12, Durham-Tsirkin discloses the method of claim 8, wherein the current execution context is a trusted execution environment (para. [0298]; discloses processor implementing a TEE).
As to claim 13, Durham-Tsirkin discloses the method of claim 8, wherein the processing device is one of: a central processing unit (CPU), a network interface controller (NIC), a data processing unit DPU, or a graphic processing unit (GPU) (Durham, para. [0113]; discloses the processor includes CPU).
As to claim 14, Durham-Tsirkin discloses the method of claim 8, wherein determining the identifier of the current execution context associated with the memory region is performed responsive to reassigning the memory region from the previous execution context to the current execution context (Durham, para. [0089]; discloses the memory manager can access an integrity check value table to determine whether the correct key domain key was used to access the data. If the wrong key domain key was used to decrypt the data, the resulting plaintext will be corrupted and will not match a corresponding integrity check value in the integrity check value table.).
As to claim 16, Durham-Tsirkin discloses the non-transitory machine-readable storage medium of claim 15, wherein the memory region is represented by one of: a cache line (Durham, para., [0090]), a memory page, a frame of a main memory, a frame of a stack, or a frame of a heap.
As to claim 17, Durham-Tsirkin discloses the non-transitory machine-readable storage medium of claim 15, wherein the current execution context is one of a thread or a process (Durham, para. [0199]; discloses virtual memory systems manage and allocate memory various processes running within the system).
As to claim 18, Durham-Tsirkin discloses the non-transitory machine-readable storage medium of claim 15, wherein the current execution context is one of: a virtual machine or a container (Durham, para. [0065).
As to claim 19, Durham-Tsirkin discloses the non-transitory machine-readable storage medium of claim 15, wherein the current execution context is a trusted execution environment (para. [0298]; discloses processor implementing a TEE).
As to claim 20, Durham-Tsirkin discloses the non-transitory machine-readable storage medium of claim 15, wherein determining the identifier of the current execution context associated with the memory region is performed responsive to reassigning the memory region from the previous execution context to the current execution context (Durham, para. [0089]; discloses the memory manager can access an integrity check value table to determine whether the correct key domain key was used to access the data. If the wrong key domain key was used to decrypt the data, the resulting plaintext will be corrupted and will not match a corresponding integrity check value in the integrity check value table.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Baumann et al. (U.S. 2013/0151846 A1) discloses providing a secure execution environment with a hosted computer are described. A security-enabled processor establishes a hardware-protected memory area with an activation state that executes only software identified by a client system. The hardware-protected memory area is inaccessible by code that executes outside the hardware-protected memory area.
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/JOE CHACKO/Primary Examiner, Art Unit 2457
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