Prosecution Insights
Last updated: October 02, 2026
Application No. 19/292,294

Method and System for Multi-Level Artificial Intelligence Supercomputer Design

Non-Final OA §103
Filed
Aug 06, 2025
Priority
May 04, 2023 — provisional 63/463,913 +6 more
Examiner
PHAM, THIERRY L
Art Unit
2654
Tech Center
2600 — Communications
Assignee
Vijay Madisetti
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
1y 8m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
574 granted / 712 resolved
+18.6% vs TC avg
Minimal +5% lift
Without
With
+5.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
8 currently pending
Career history
722
Total Applications
across all art units

Statute-Specific Performance

§101
12.7%
-27.3% vs TC avg
§103
42.0%
+2.0% vs TC avg
§102
28.9%
-11.1% vs TC avg
§112
7.1%
-32.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 712 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status ● The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . ● This action is responsive to the following communication: RCE filed on 6/16/2026. ● Claims 1-3, 5-8, 10-13, and 15 are currently pending; claims 4, 9,14 have been canceled. Continued Examination Under 37 CFR 1.114 ● A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/16/2026 has been entered. Response to Arguments ● Applicant’s arguments with respect to claim(s) 1, 6, 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5-8, 10-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gray et al (US 11769017) in view of Sivakumar et al (US 20220345353). Regarding claim 1, Gray discloses a method for in-memory processing of h-LLM data comprising: receiving an input data stream (receive a query, fig. 2); operating a data receiver operable to divide the input data stream into a plurality of data batches (divide/separate an inputted query into batches, figs.2,3, and to process said batches in parallel for fasting processing, pars. 121, 122) by aggregating the data over aggregation period (duration of time, par. 55) during tied to a fixed scheduled for batch processing; processing the plurality of data batches using a processing layer (processing batches using different family of LLM architectures/layers/models, pars. 121-122), the processing layer comprising a plurality of h-LLMs operating at least partially in volatile memory (e.g. Random Access Memory, par. 131), each h-LLM of the plurality of the h-LLM being trained with different training set (training data, col. 3, lines 20-35), the processing layer being configured to process the plurality of data batches in parallel (parallel processing, pars. 121-122) using the plurality of h-LLMs; and producing a plurality of processed data batches (outputting processed data from batches, figs. 2-5, pars. 121-122) from an output of the processing layer. Gray fails to teach and/or suggest each learning model of the plurality of models are being trained with a different training dataset. Sivakumar, in the same field of machine learning models, teaches a well-known example wherein each learning model of the plurality of learning models are being trained with a different training dataset (each learning model is being trained with different training dataset, fig. 2, 60, 91). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention by modifying learning models of Gray to include methods/steps of training each model using different training dataset as taught by Sivakumar to improve accuracy of each models (par. 92 of Sivakumar). Therefore, it would have been obvious to combine Gray with Sivakumar to obtain the invention as specified in claim 1. Regarding claim 2, Gray further discloses the method of claim 1 wherein the volatile memory comprises at least one of random-access memory (RAM) devices (RAM 830, par. 131), static random-access memory (SRAM) devices, dynamic random-access memory (DRAM) devices, magnetoresistive random- access memory (MRAM) devices, and non-volatile random-access memory (NVRAM) devices. Regarding claim 3, Gray further discloses the method of claim 1 wherein the volatile memory consists of one of random-access memory (RAM) devices (RAM 830, par. 131), static random-access memory (SRAM) devices, dynamic random-access memory (DRAM) devices, magnetoresistive random- access memory (MRAM) devices, and non-volatile random-access memory (NVRAM) devices. Regarding claim 5, Gray further discloses the method of claim 1 wherein the processing is performed entirely within the volatile memory (RAM 830, par. 131). Regarding claims 6-8, 10-13, 15 recite limitations that are similar and in the same scope of invention as to those in claims 1-3, 5 above; therefore, claims 6-8, 10-13, 15 are rejected for the same rejection rationale/basis as described in claims 1-3, 5. Conclusion ● US 20210225369 to Hu et al, teaches methods/steps of training each language model with different training datasets. ● US 20220351004 to Kanter et al, teaches methods/steps of training each language model with different training datasets. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIERRY L PHAM whose telephone number is (571)272-7439. The examiner can normally be reached M-F, 11-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hai Phan can be reached at (571)272-6338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THIERRY L PHAM/Primary Examiner, Art Unit 2654
Read full office action

Prosecution Timeline

Show 7 earlier events
Apr 23, 2026
Interview Requested
May 19, 2026
Applicant Interview (Telephonic)
May 19, 2026
Response after Non-Final Action
May 20, 2026
Examiner Interview Summary
Jun 16, 2026
Request for Continued Examination
Jun 18, 2026
Response after Non-Final Action
Sep 01, 2026
Non-Final Rejection mailed — §103
Sep 14, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
86%
With Interview (+5.0%)
2y 10m (~1y 8m remaining)
Median Time to Grant
High
PTA Risk
Based on 712 resolved cases by this examiner. Grant probability derived from career allowance rate.

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