DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 06/25/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 11, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al (US 2021/0359073 A1) in view of Kim et al (US 2020/0118490 A1).
Claim 1, Cha (Fig. 1-16) discloses a display apparatus (1; Fig. 1; wherein discloses a display device 1), comprising a photosensitive device (40; Fig. 2; Paragraph [0056]; wherein discloses a component 40 which may include a camera) and a display substrate (100; Fig. 3) having a display area (DA; Fig. 3; wherein discloses a display area DA; Paragraph [0053]) and a bezel area (DPA; Fig. 3; wherein discloses a peripheral area DPA which is surrounding the display area DA; Paragraph [0053]) surrounding the display area (DA; Fig. 3), wherein the display area (DA; Fig. 3) comprises a first display area (CA; Fig. 3) and a second display area (MDA; Fig. 3) on a side of (Paragraph [0054]; wherein discloses “the component area CA may be arranged in any suitable location according to the design of the display device 1, for example, at one side of the main display area MDA, which has a quadrangular shape, for example, on the top right side or the top left side”) the first display area (CA; Fig. 3);
the first display area (CA; Fig. 2, 5A, and 5B) has a light transmittance higher (TA; Fig. 2, 5A, and 5B; Paragraph [0056]; wherein discloses “when light is allowed to pass through the component area CA, a light transmittance may be 10% or more, more preferably, 40% or more, 25% or more, 50% or more, 85% or more, or 90% or more”) than a light transmittance of the second display area (MDA; Fig. 2 and 4; wherein figure shows the main display area does not include the transmission area TA);
the first display area (CA; Fig. 5A and 5B) comprises a plurality of pixel units (PG; Fig. 5A and 5B; Paragraph [0104]) distributed in an array (Fig. 9; Paragraph [0178]), each of the plurality of pixel units (PG; Fig. 5A and 5B) comprising a first subpixel (Pr; Fig. 5A and 5B) and a second subpixel (Pg; Fig. 5A and 5B) emitting different colors of light (Paragraph [0104]; wherein discloses “a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb”); and
wherein the photosensitive device (40; Fig. 2; Paragraph [0056]; wherein discloses a component 40 which may include a camera) is on a side of the display substrate (100; Fig. 2; wherein figure shows the component 40 arranged below the substrate 100), and in the first display area (CA; Fig. 2) of the display substrate (100; Fig. 1).
Cha does not expressly disclose the first display area comprises a first initialization voltage line and a second initialization voltage line, wherein the first initialization voltage line is electrically connected to the first subpixel, and not electrically connected to the second subpixel, the second initialization voltage line is electrically connected to the second subpixel and not electrically connected to the first subpixel, light-emitting devices of the first subpixel and the second subpixel are both in the first display area and neither in the second display area, and the first initialization voltage line and the second initialization voltage line are configured to receive different initialization voltages.
Kim (Fig. 1A-20) discloses the first display area (AA2 and AA3; Fig. 3 and 18; wherein figure shows an area (AA2 and AA3) on a side of a second area (AA1)) comprises a first initialization voltage line (VINT3; Fig. 18) and a second initialization voltage line (VINT2; Fig. 18), wherein the first initialization voltage line (VINT3; Fig. 18) is electrically connected to the first subpixel (PXL3; Fig. 18), and not electrically connected to the second subpixel (PXL2; Fig. 18; wherein figure shows PXL2 receiving VINT2 different than VINT3), the second initialization voltage line (VINT2; Fig. 18) is electrically connected to the second subpixel (PXL2; Fig. 3) and not electrically connected to the first subpixel (PXL3; Fig. 18; wherein figure shows PXL3 receiving VINT3 different than VINT2), light-emitting devices of the first subpixel (PXL3; Fig. 18) and the second subpixel (PXL2; Fig. 18) are both in the first display area (AA3 and AA2; Fig. 18) and neither in the second display area (AA1; Fig. 3 and 18; wherein figures show a third pixel PXL1 in the second area AA1 connected to a different initialization voltage VINT1), and the first initialization voltage line (Vint3; Fig. 18) and the second initialization voltage line (Vint2; Fig. 18) are configured to receive different initialization voltages (Paragraph [0246]; wherein discloses different initialization power supplies).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha’s display apparatus by applying different initialization voltages, as taught by Kim, so to use a display apparatus with different initialization voltages for providing a display device and a driving method thereof for improving a luminance difference (Paragraph [0006]).
Claim 2, Cha (Fig. 1-16) discloses wherein the pixel unit (PG; Fig. 5A and 5B; Paragraph [0104]) further comprises a third subpixel (Pa; Fig. 9; wherein figure shows the third subpixel Pa in the row is connected to the second initialization line VL2) emitting light of a color different (Pb; Fig. 5A and 5B; Paragraph [0104]; wherein discloses “a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb”) from the colors of both the first subpixel (Pr; Fig. 5A and 5B) and the second subpixel (Pg; Fig. 5A and 5B), and the third subpixel (Pa; Fig. 9; wherein figure shows the third subpixel Pa in the row is connected to the second initialization line VL2) is electrically connected to the second initialization voltage line (VL2; Fig. 9).
Claim 11, Cha (Fig. 1-16) discloses wherein the first subpixel is a green subpixel (Pg; Fig. 5A and 5B), the second subpixel is a red subpixel (Pr; Fig. 5A and 5B), and the third subpixel is a blue subpixel (Pb; Fig. 5A and 5B).
Claim 13, Cha (Fig. 1-16) discloses wherein the first display area (CA; Fig. 5A and 5B) has a resolution lower (Paragraph [0057]; wherein discloses “An image displayed in the component area CA includes an auxiliary image and may have a resolution less than an image displayed in the main display area MDA”; Paragraph [0083]) than a resolution of the second display area (MDA; Fig. 4), or the first display area and the second display area have substantially the same resolution.
Claim 14, Cha (Fig. 1-16) discloses wherein the first display area (CA; Fig. 5A and 5B) has a shape comprising at least one of a circular shape, an elliptical shape, a rectangular shape, or a polygonal shape (Paragraph [0054]; wherein discloses “the component area CA may have various shapes such as a circle, an ellipse, a polygon including a quadrangle, a hexagon, and an octagon, a star shape, or a diamond shape”).
Claim 15, Cha (Fig. 1-16) discloses wherein the photosensitive device (40; Fig. 2) comprises a camera module (Paragraph [0056]; wherein discloses “The component 40 may include a camera”).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cha et al (US 2021/0359073 A1) in view of Kim et al (US 2020/0118490 A1) as applied to claim 2 above, and further in view of Chen (US 2022/0310731 A1).
Claim 3, Cha in view of Kim discloses the display apparatus according to claim 2.
Cha in view of Kim does not expressly disclose comprising a base substrate, a first gate metal layer, a second gate metal layer, and a source/drain metal layer which are sequentially stacked;
wherein the first initialization voltage line and the second initialization voltage line are in the same layer as the first gate metal layer; or,
the first initialization voltage line and the second initialization voltage line are in the same layer as the second gate metal layer; or,
one of the first initialization voltage line and the second initialization voltage line is in the same layer as the first gate metal layer, while the other of the first initialization voltage line and the second initialization voltage line is in the same layer as the second gate metal layer.
Chen (Fig. 1-11) discloses comprising a base substrate (100; Fig. 3; Paragraph [0058]; wherein discloses a substrate 100), a first gate metal layer (400; Paragraph [0058]; wherein discloses a first metal layer; or 500; Paragraph [0058]; wherein discloses a second metal layer), a second gate metal layer (500; Paragraph [0058]; wherein discloses a second metal layer; or 700; Paragraph [0058]; wherein discloses a third metal layer), and a source/drain metal layer (800; Fig. 3; Paragraph [0058]; wherein discloses a first source and drain layer) which are sequentially stacked (Fig. 3; wherein discloses a film layer structure of the display panel);
wherein the first initialization voltage line (501; Fig. 7; wherein figure shows first line 501 connected to a hole 005 to the transistor T4 shown in figure 8; Paragraph [0068]) and the second initialization voltage line (501; Fig. 7; wherein figure shows a second line 501 connected to a hole 013 to the transistor T7 shown in figure 8) are in the same layer (500; Fig. 7) as the first gate metal layer (500; Fig. 3; Paragraph [0058]; wherein discloses a second metal layer; wherein figure 3 shows for the second transistor a first gate in the 500 layer and a second gate in the 700 layer and finally both source and drain in the 800 layer); or,
the first initialization voltage line (501; Fig. 7; wherein figure shows first line 501 connected to a hole 005 to the transistor T4 shown in figure 8; Paragraph [0068]) and the second initialization voltage line (501; Fig. 7; wherein figure shows a second line 501 connected to a hole 013 to the transistor T7 shown in figure 8) are in the same layer (500; Fig. 7) as the second gate metal layer (500; Fig. 3; Paragraph [0058]; wherein discloses a second metal layer; wherein figure 3 shows for the first transistor a first gate in the 400 layer and a second gate in the 500 layer and finally both source and drain in the 800 layer); or,
one of the first initialization voltage line and the second initialization voltage line is in the same layer as the first gate metal layer, while the other of the first initialization voltage line and the second initialization voltage line is in the same layer as the second gate metal layer.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying a layering method, as taught by Chen, so to use a display apparatus with a layering method for providing so that the pixel driving circuit is more stable and the display effect of the display panel is improved (Paragraph [0028]).
Claims 4, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al (US 2021/0359073 A1) in view of Kim et al (US 2020/0118490 A1) as applied to claim 2 above, and further in view of An et al (US 2022/0366847 A1).
Claim 4, Cha (Fig. 1-16) discloses wherein each of the first (Pr; Fig. 5A and 5B), second (Pg; Fig. 5A and 5B), and third subpixels (Pb; Fig. 5A and 5B) comprise a light-emitting device (OLED; Fig. 7), and a driving circuit (PC/PC’; Fig. 7; Paragraph [0161]);
the driving circuit (PC/PC’; Fig. 7; Paragraph [0161]) comprises a first initialization transistor (T4; Fig. 7), a second initialization transistor (T7; Fig. 7), a driving transistor (T1; Fig. 7), a data writing transistor (T2; Fig. 7), a threshold compensation transistor (T3; Fig. 7), a first light emission control transistor (T5; Fig. 7), a second light emission control transistor (T6; Fig. 7), and a storage capacitor (Cst; Fig. 7);
a gate of the first initialization transistor (T4; Fig. 7) is electrically connected to a reset signal line (SS3/SL3; Fig. 7), a first electrode of a first initialization transistor (T4; Fig. 7) in a driving circuit (PC/PC”; Fig. 7) corresponding to the first subpixel (Pr; Fig. 5A and 5B) is electrically connected to the first initialization voltage line (Vint1/VL1; Fig. 7), and a second electrode of the first initialization transistor (T4; Fig. 7) is electrically connected to (N2; Fig. 7) a gate of the driving transistor (T1; Fig. 7);
a gate of the second initialization transistor (T7; Fig. 7) is electrically connected to a scanning signal line (SS4/SL4; Fig. 7), first electrodes of second initialization transistors (T7; Fig. 7) in the driving circuits (PC/PC’; Fig. 7) corresponding to the second subpixel (Pg; Fig. 5A and 5B) and the third subpixel (Pb; Fig. 5A and 5B) are each electrically connected to the second initialization voltage line (Vint2/VL2; Fig. 7), and a second electrode of the second initialization transistor (T7; Fig. 7) is electrically connected to an anode of the light-emitting device (OLED; Fig. 7);
a gate of the first light emission control transistor (T5; Fig. 7) is electrically connected to a light emission control line (EN/EL; Fig. 7), a first electrode of the first light emission control transistor (T5; Fig. 7) is electrically connected to a first power supply line (ELVDD/PL; Fig. 7), and a second electrode of the first light emission control transistor (T5; Fig. 7) is electrically connected to a first electrode of the driving transistor (N1/T1; Fig. 7);
a gate of the second light emission control transistor (T6; Fig. 7) is electrically connected to the light emission control line (EN/EL; Fig. 7), a first electrode of the second light emission control transistor (T6; Fig. 7) is electrically connected to a second electrode of the driving transistor (N3/T1; Fig. 7), and a second electrode of the second light emission control transistor (T6; Fig. 7) is electrically connected to the anode of the light-emitting device (OLED; Fig. 7);
a cathode of the light-emitting device (OLED; Fig. 7) is electrically connected to a second power supply line (ELVSS; Fig. 7);
a gate of the threshold compensation transistor (T3; Fig. 7) is electrically connected to the scanning signal line (SS3/SL2; Fig. 7), a first electrode of the threshold compensation transistor (T3; Fig. 7) is electrically connected to the gate of the driving transistor (N2/T1; Fig. 7), and a second electrode of the threshold compensation transistor (T3; Fig. 7) is electrically connected to the second electrode of the driving transistor (N3/T1; Fig. 7);
a gate of the data writing transistor (T2; Fig. 7) is electrically connected to the scanning signal line (SS1/SL1; Fig. 7), a first electrode of the first data writing transistor (T3; Fig. 7) is electrically connected to a data signal line (DATA/DL; Fig. 7), and a second electrode of the data writing transistor (T3; Fig. 7) is electrically connected to the first electrode of the driving transistor (N1/T1; Fig. 7); and
a first electrode of the storage capacitor (Cst; Fig. 7) is electrically connected to the first power supply line (ELVDD/PL: Fig. 7), and a second electrode of the storage capacitor (Cst; Fig. 7) is electrically connected to the gate of the driving transistor (N2/T1; Fig. 7).
Cha in view of Kim does not expressly disclose wherein each of the first, second, and third subpixels comprise a light-emitting device, and a driving circuit in the bezel area or the second display area;
first electrodes of first initialization transistors in driving circuits corresponding to the second subpixel and the third subpixel are each electrically connected to the second initialization voltage line; and
a first electrode of a second initialization transistor in the driving circuit corresponding to the first subpixel is electrically connected to the first initialization voltage line.
An (Fig. 1-25) discloses wherein each of the first (PX1; Fig. 18), second (PX2; Fig. 18), and third subpixels (PX3; Fig. 18) comprise a light-emitting device (DE1; Fig. 4; DE2; Fig. 5), and a driving circuit (PC2; Fig. 14) in the bezel area (PA; Fig. 14; Paragraph [0250]) or the second display area (PC2; Fig. 18);
first electrodes of first initialization transistors (T42; Fig. 5) in driving circuits (PC2; Fig. 5) corresponding to the second subpixel (PX2; Fig. 2 and 3) and the third subpixel (PX3; Fig. 18; wherein figure shows both PX2 and PX3 connected to the same initialization line VL2”a) are each electrically connected to the second initialization voltage line (VL2”a; Fig. 18; VINT2; Fig. 2 and 3); and
a first electrode of a second initialization transistor (T71; Fig. 4) in the driving circuit (PC1; Fig. 4) corresponding to the first subpixel (PX1; Fig. 2 and 3; PX1; Fig. 18; wherein figure shows PX1 connected to the initialization line VL1”a) is electrically connected to the first initialization voltage line (VL1”a; Fig. 18; VINT1; Fig. 2 and 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying driving circuit, as taught by An, so to use a display apparatus with driving circuit for improving the display quality of a display apparatus having plural display areas having different image resolution capabilities (Paragraph [0006]).
Claim 10, An (Fig. 1-25) discloses wherein the driving circuit (PC2; Fig. 14) is in a part of the bezel area (PA; Fig. 14; Paragraph [0250]) adjacent to the first display area (AR2; Fig. 14); or,
the second display area (AR1; Fig. 18) has a transition area (MA; Fig. 18) adjacent to the first display area (CA; Fig. 18), and the driving circuit (PC2; Fig. 18) is in the transition area (M; Fig. 18).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying driving circuit, as taught by An, so to use a display apparatus with driving circuit for improving the display quality of a display apparatus having plural display areas having different image resolution capabilities (Paragraph [0006]).
Claim 12, An (Fig. 1-25) discloses further comprises at least one transparent wiring layer (TWL; Fig. 13; Paragraph [0240]; wherein discloses “The connection line TWL may include a transparent conductive material”) between the driving circuit (PC2; Fig. 13) and the anode of the light-emitting device (DE2; Fig. 13), and the driving circuit (PC2; Fig. 13) and the anode (DE2; Fig. 13) are electrically connected via a transparent wire in the transparent wiring layer (TWL; Fig. 13; Paragraph [0240]; wherein discloses “The connection line TWL may include a transparent conductive material”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying driving circuit, as taught by An, so to use a display apparatus with driving circuit for improving the display quality of a display apparatus having plural display areas having different image resolution capabilities (Paragraph [0006]).
Claims 5, 7, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al (US 2021/0359073 A1) in view of Kim et al (US 2020/0118490 A1) as applied to claim 1 above, and further in view of Jun et al (US 2014/0118409 A1).
Claim 5, Cha (Fig. 1-16) discloses wherein the pixel unit (PG; Fig. 5A and 5B) further comprises a third subpixel (Pb; Fig. 5A and 5B) emitting light of a color different (Pb; Fig. 5A and 5B; Paragraph [0104]; wherein discloses “a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb”) from the colors of both the first subpixel (Pr; Fig. 5A and 5B) and the second subpixel (Pg; Fig. 5a and 5B).
Cha in view of Kim does not expressly disclose the first display area further comprises a third initialization voltage line electrically connected to the third subpixel and configured to receive an initialization voltage different from the initialization voltages of the first initialization voltage line and the second initialization voltage line.
Jun (Fig. 1-8) discloses the first display area (10; Fig. 2) further comprises a third initialization voltage line (BV; Fig. 2; BVinit; Fig. 4) electrically connected to the third subpixel (B_PX; Fig. 3) and configured to receive an initialization voltage (BV; Fig. 2; BVinit; Fig. 4; BVinit; Fig. 8) different from the initialization voltages of the first initialization voltage line (RV; Fig. 2; RVinit; Fig. 4; RVinit; Fig. 8) and the second initialization voltage line (GV; Fig. 2; GVinit; Fig. 4; GVinit; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying a third initialization voltage, as taught by Jun, so to use a display apparatus with a third initialization voltage for provide a method of driving a display device capable of compensating for gray spots to implement high-quality display images by controlling the supply of an initialization (or initializing) voltage to pixels displaying each color of red, green, and blue (RGB) and capable of reducing a time required for compensating for variations (or deviations) in threshold voltages of the driving transistors of pixels displaying each color (Paragraph [0015]).
Claim 7, Cha (Fig. 1-16) discloses wherein the first subpixel is a green subpixel (Pg; Fig. 5A and 5B), the second subpixel is a red subpixel (Pr; Fig. 5A and 5B), and the third subpixel is a blue subpixel (Pb; Fig. 5A and 5B).
Claim 16, Cha (Fig. 1-16) discloses a method for driving (Paragraph [0168]; wherein discloses “A third scan signal SS3 may be applied at a timing prior to a first scan signal SS1”; Paragraph [0170]; wherein discloses “A fourth scan signal SS4 may be applied at a timing prior to a first scan signal SS1 or applied at a timing later than a first scan signal SS1”; therefore prior to a first scan signal SS1 both initialization transistors are enabled) the display apparatus (1; Fig. 1) according to claim 1 (see rejection to claim 1 above).
Cha in view of Kim does not expressly disclose comprising:
in an initialization stage, loading a first initialization voltage to the first subpixel through the first initialization voltage line, and loading a second initialization voltage to the second subpixel through the second initialization voltage line;
wherein the first initialization voltage is greater than the second initialization voltage.
Jun (Fig. 1-8) discloses comprising:
in an initialization stage (Fig. 8; wherein prior to T10 the signal S(n-1) enables the initialization transistor (M4; Fig. 5)), loading a first initialization voltage (BVinit; Fig. 8) to the first subpixel (B_PX; Fig. 3) through the first initialization voltage line (BV; Fig. 3), and loading a second initialization voltage (GVinit; Fig. 8) to the second subpixel (G_PX; Fig. 3) through the second initialization voltage line (GV; Fig. 3);
wherein the first initialization voltage (BVinit; Fig. 8) is greater than the second initialization voltage (GVinit; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying a third initialization voltage, as taught by Jun, so to use a display apparatus with a third initialization voltage for provide a method of driving a display device capable of compensating for gray spots to implement high-quality display images by controlling the supply of an initialization (or initializing) voltage to pixels displaying each color of red, green, and blue (RGB) and capable of reducing a time required for compensating for variations (or deviations) in threshold voltages of the driving transistors of pixels displaying each color (Paragraph [0015]).
Claim 17, Cha (Fig. 1-16) discloses further comprising:
in the initialization stage (Paragraph [0170]; wherein discloses “A fourth scan signal SS4 may be applied at a timing prior to a first scan signal SS1 or applied at a timing later than a first scan signal SS1”), loading the second initialization voltage (Vinit2; Fig. 7) to the third subpixel (Pa; Fig. 9; wherein figure shows the third subpixel Pa in the row is connected to the second initialization line VL2) through the second initialization voltage line (VL2; Fig. 9).
Claim 18, Jun (Fig. 1-8) discloses wherein the first initialization voltage (BVinit; Fig. 8) is greater than the second initialization voltage (GVinit; Fig. 8) by substantially 0.5V (Paragraph [0092]; wherein discloses each respective color can have a respective initialization voltage based on a calculation; therefore since the voltages are variable the Examiner believes that the prior art reference of Jun’s embodiment would read on a broad range of voltage differences).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying a third initialization voltage, as taught by Jun, so to use a display apparatus with a third initialization voltage for provide a method of driving a display device capable of compensating for gray spots to implement high-quality display images by controlling the supply of an initialization (or initializing) voltage to pixels displaying each color of red, green, and blue (RGB) and capable of reducing a time required for compensating for variations (or deviations) in threshold voltages of the driving transistors of pixels displaying each color (Paragraph [0015]).
Claim 19, Cha (Fig. 1-16) discloses wherein each of the plurality of pixel units (PG; Fig. 5A and 5B) in the first display area (CA; Fig. 5A and 5B) further comprises a third subpixel (Pb; Fig. 5A and 5B) emitting light of a color different (Paragraph [0104]; wherein discloses “a pixel group PG may include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb”) from the colors of both the first subpixel (Pr; Fig. 5A and 5B) and the second subpixel (Pg; Fig. 5A and 5B).
Jun (Fig. 1-8) discloses the display area (10; Fig. 1) of the display substrate (Paragraph [0052]; wherein discloses a base substrate) further comprises a third initialization voltage line (RV; Fig. 3) electrically connected to the third subpixel (R_PX; Fig. 3) and configured to receive an initialization voltage (RVinit; Fig. 8) different from the initialization voltages of the first initialization voltage line (BVinit; Fig. 8; BV; Fig. 3) and the second initialization voltage line (GVinit; Fig. 8; GV; Fig. 3); and
the method further comprises:
in the initialization stage (Fig. 8; wherein prior to T10 the signal S(n-1) enables the initialization transistor (M4; Fig. 5)), loading a third initialization voltage (RVinit; Fig. 8) to the third subpixel (R_PX; fig. 3) through the third initialization voltage line (RV; Fig. 3);
wherein the third initialization voltage (RVinit; Fig. 8) is less than the second initialization voltage (GVinit; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying a third initialization voltage, as taught by Jun, so to use a display apparatus with a third initialization voltage for provide a method of driving a display device capable of compensating for gray spots to implement high-quality display images by controlling the supply of an initialization (or initializing) voltage to pixels displaying each color of red, green, and blue (RGB) and capable of reducing a time required for compensating for variations (or deviations) in threshold voltages of the driving transistors of pixels displaying each color (Paragraph [0015]).
Claim 20, Jun (Fig. 1-8) discloses wherein the first initialization voltage (BVinit; Fig. 8) is greater than the second initialization voltage (GVinit; Fig. 8) by substantially 0.2V (Paragraph [0092]; wherein discloses each respective color can have a respective initialization voltage based on a calculation; therefore since the voltages are variable the Examiner believes that the prior art reference of Jun’s embodiment would read on a broad range of voltage differences), and the second initialization voltage (GVinit; Fig. 8) is greater than the third initialization voltage (RVinit; Fig. 8) by substantially 0.3V (Paragraph [0092]; wherein discloses each respective color can have a respective initialization voltage based on a calculation; therefore since the voltages are variable the Examiner believes that the prior art reference of Jun’s embodiment would read on a broad range of voltage differences).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim’s display apparatus by applying a third initialization voltage, as taught by Jun, so to use a display apparatus with a third initialization voltage for provide a method of driving a display device capable of compensating for gray spots to implement high-quality display images by controlling the supply of an initialization (or initializing) voltage to pixels displaying each color of red, green, and blue (RGB) and capable of reducing a time required for compensating for variations (or deviations) in threshold voltages of the driving transistors of pixels displaying each color (Paragraph [0015]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cha et al (US 2021/0359073 A1) in view of Kim et al (US 2020/0118490 A1) and Jun et al (US 2014/0118409 A1) as applied to claim 5 above, and further in view of Chen (US 2022/0310731 A1).
Claim 6, Cha in view of Kim and Jun discloses the display apparatus according to claim 5.
Cha in view of Kim and Jun does not expressly disclose comprising a base substrate, a first gate metal layer, a second gate metal layer, and a source/drain metal layer which are sequentially stacked;
wherein the first initialization voltage line, the second initialization voltage line and the third initialization voltage line are in the same layer as the first gate metal layer; or,
the first initialization voltage line, the second initialization voltage line and the third initialization voltage line are in the same layer as the second gate metal layer; or,
two of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line are arranged in the same layer as the first gate metal layer, while the rest one of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line is arranged in the same layer as the second gate metal layer.
Chen (Fig. 1-11) discloses comprising a base substrate (100; Fig. 3; Paragraph [0058]; wherein discloses a substrate 100), a first gate metal layer (400; Paragraph [0058]; wherein discloses a first metal layer; or 500; Paragraph [0058]; wherein discloses a second metal layer), a second gate metal layer (500; Paragraph [0058]; wherein discloses a second metal layer; or 700; Paragraph [0058]; wherein discloses a third metal layer), and a source/drain metal layer (800; Fig. 3; Paragraph [0058]; wherein discloses a first source and drain layer) which are sequentially stacked (Fig. 3; wherein discloses a film layer structure of the display panel);
wherein the first initialization voltage line (501; Fig. 7; wherein figure shows first line 501 connected to a hole 005 to the transistor T4 shown in figure 8; Paragraph [0068]), the second initialization voltage line (501; Fig. 7; wherein figure shows a second line 501 connected to a hole 013 to the transistor T7 shown in figure 8) and the third initialization voltage line (one of the remaining 501; Fig. 7; wherein figure shows a third line 501 connected to a hole 013 to the transistor T7 shown in figure 8 and a fourth line 501 connected to a hole 005 to the transistor T4 shown in figure 8) are in the same layer (500; Fig. 7) as the first gate metal layer (500; Fig. 3; Paragraph [0058]; wherein discloses a second metal layer; wherein figure 3 shows for the second transistor a first gate in the 500 layer and a second gate in the 700 layer and finally both source and drain in the 800 layer); or,
the first initialization voltage line (501; Fig. 7; wherein figure shows first line 501 connected to a hole 005 to the transistor T4 shown in figure 8; Paragraph [0068]), the second initialization voltage line (501; Fig. 7; wherein figure shows a second line 501 connected to a hole 013 to the transistor T7 shown in figure 8) and the third initialization voltage line line (one of the remaining 501; Fig. 7; wherein figure shows a third line 501 connected to a hole 013 to the transistor T7 shown in figure 8 and a fourth line 501 connected to a hole 005 to the transistor T4 shown in figure 8) are in the same layer (500; Fig. 7) as the second gate metal layer (500; Fig. 3; Paragraph [0058]; wherein discloses a second metal layer; wherein figure 3 shows for the first transistor a first gate in the 400 layer and a second gate in the 500 layer and finally both source and drain in the 800 layer); or,
two of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line are arranged in the same layer as the first gate metal layer, while the rest one of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line is arranged in the same layer as the second gate metal layer.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim and Jun’s display apparatus by applying a layering method, as taught by Chen, so to use a display apparatus with a layering method for providing so that the pixel driving circuit is more stable and the display effect of the display panel is improved (Paragraph [0028]).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al (US 2021/0359073 A1) in view of Kim et al (US 2020/0118490 A1) and Jun et al (US 2014/0118409 A1) as applied to claim 5 above, and further in view of An et al (US 2022/0366847 A1).
Claim 8, Cha (Fig. 1-16) discloses wherein each of the first (Pr; Fig. 5A and 5B), second (Pg; Fig. 5A and 5B), and third subpixels (Pb; Fig. 5A and 5B) comprise a light-emitting device (OLED; Fig. 7), and a driving circuit (PC/PC’; Fig. 7; Paragraph [0161]);
the driving circuit (PC/PC’; Fig. 7; Paragraph [0161]) comprises a first initialization transistor (T4; Fig. 7), a second initialization transistor (T7; Fig. 7), a driving transistor (T1; Fig. 7), a data writing transistor (T2; Fig. 7), a threshold compensation transistor (T3; Fig. 7), a first light emission control transistor (T5; Fig. 7), a second light emission control transistor (T6; Fig. 7), and a storage capacitor (Cst; Fig. 7);
a gate of the first initialization transistor (T4; Fig. 7) is electrically connected to a reset signal line (SS3/SL3; Fig. 7), a first electrode of a first initialization transistor (T4; Fig. 7) in a driving circuit (PC/PC”; Fig. 7) corresponding to the first subpixel (Pr; Fig. 5A and 5B) is electrically connected to the first initialization voltage line (Vint1/VL1; Fig. 7), and a second electrode of the first initialization transistor (T4; Fig. 7) is electrically connected to (N2; Fig. 7) a gate of the driving transistor (T1; Fig. 7);
a gate of the second initialization transistor (T7; Fig. 7) is electrically connected to a scanning signal line (SS4/SL4; Fig. 7), first electrodes of second initialization transistors (T7; Fig. 7) in the driving circuits (PC/PC’; Fig. 7) corresponding to the second subpixel (Pg; Fig. 5A and 5B) is electrically connected to the second initialization voltage line (Vint2/VL2; Fig. 7), and a second electrode of the second initialization transistor (T7; Fig. 7) is electrically connected to an anode of the light-emitting device (OLED; Fig. 7);
a gate of the first light emission control transistor (T5; Fig. 7) is electrically connected to a light emission control line (EN/EL; Fig. 7), a first electrode of the first light emission control transistor (T5; Fig. 7) is electrically connected to a first power supply line (ELVDD/PL; Fig. 7), and a second electrode of the first light emission control transistor (T5; Fig. 7) is electrically connected to a first electrode of the driving transistor (N1/T1; Fig. 7);
a gate of the second light emission control transistor (T6; Fig. 7) is electrically connected to the light emission control line (EN/EL; Fig. 7), a first electrode of the second light emission control transistor (T6; Fig. 7) is electrically connected to a second electrode of the driving transistor (N3/T1; Fig. 7), and a second electrode of the second light emission control transistor (T6; Fig. 7) is electrically connected to the anode of the light-emitting device (OLED; Fig. 7);
a cathode of the light-emitting device (OLED; Fig. 7) is electrically connected to a second power supply line (ELVSS; Fig. 7);
a gate of the threshold compensation transistor (T3; Fig. 7) is electrically connected to the scanning signal line (SS3/SL2; Fig. 7), a first electrode of the threshold compensation transistor (T3; Fig. 7) is electrically connected to the gate of the driving transistor (N2/T1; Fig. 7), and a second electrode of the threshold compensation transistor (T3; Fig. 7) is electrically connected to the second electrode of the driving transistor (N3/T1; Fig. 7);
a gate of the data writing transistor (T2; Fig. 7) is electrically connected to the scanning signal line (SS1/SL1; Fig. 7), a first electrode of the first data writing transistor (T3; Fig. 7) is electrically connected to a data signal line (DATA/DL; Fig. 7), and a second electrode of the data writing transistor (T3; Fig. 7) is electrically connected to the first electrode of the driving transistor (N1/T1; Fig. 7); and
a first electrode of the storage capacitor (Cst; Fig. 7) is electrically connected to the first power supply line (ELVDD/PL: Fig. 7), and a second electrode of the storage capacitor (Cst; Fig. 7) is electrically connected to the gate of the driving transistor (N2/T1; Fig. 7).
Cha in view of Kim and Jun does not expressly disclose wherein each of the first, second, and third subpixels comprise a light-emitting device, and a driving circuit in the bezel area or the second display area;
a first electrode of a first initialization transistor in a driving circuit corresponding to the second subpixel is electrically connected to the second initialization voltage line, a first electrode of a first initialization transistor in a driving circuit corresponding to the third subpixel is electrically connected to the third initialization voltage line;
a first electrode of a second initialization transistor in the driving circuit corresponding to the first subpixel is electrically connected to the first initialization voltage line, and a first electrode of a second initialization transistor in the driving circuit corresponding to the third subpixel is electrically connected to the third initialization voltage line.
An (Fig. 1-25) discloses wherein each of the first (PX1; Fig. 18; wherein figure shows a first pixel connected to VL1”a), second (PX3 or PX2; Fig. 18; wherein figure shows a second pixel connected to VL2”a), and third subpixels (PX3 or PX2; Fig. 18; wherein figure shows a third pixel connected to VL2”b) comprise a light-emitting device (DE1; Fig. 4; DE2; Fig. 5) , and a driving circuit (PC2; Fig. 14) in the bezel area (PA; Fig. 14; Paragraph [0250]) or the second display area (PC2; Fig. 18);
a first electrode of a first initialization transistor (T42; Fig. 5) in a driving circuit (PC2; Fig. 5) corresponding to the second subpixel (PX3 or PX2; Fig. 18; wherein figure shows a second pixel connected to VL2”a) is electrically connected to the second initialization voltage line (VL2”a; Fig. 18), a first electrode of a first initialization transistor (T42; Fig. 5) in a driving circuit (PC2; Fig. 5) corresponding to the third subpixel (PX3 or PX2; Fig. 18; wherein figure shows a third pixel connected to VL2”b) is electrically connected to the third initialization voltage line (VL2”b; Fig. 18);
a first electrode of a second initialization transistor (T71; Fig. 4) in the driving circuit (PC1; Fig. 4) corresponding to the first subpixel (PX1; Fig. 18) is electrically connected to the first initialization voltage line (VL1”a; Fig. 18), and a first electrode of a second initialization transistor (T72; Fig. 5) in the driving circuit (PC2; Fig. 5) corresponding to the third subpixel (PX3 or PX2; Fig. 18; wherein figure shows a third pixel connected to VL2”b) is electrically connected to the third initialization voltage line (VL2”b; Fig. 18).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim and Jun’s display apparatus by applying driving circuit, as taught by An, so to use a display apparatus with driving circuit for improving the display quality of a display apparatus having plural display areas having different image resolution capabilities (Paragraph [0006]).
Claim 9, An (Fig. 1-25) discloses wherein the driving circuit (PC2; Fig. 14) is in a part of the bezel area (PA; Fig. 14; Paragraph [0250]) adjacent to the first display area (AR2; Fig. 14); or,
the second display area (AR1; Fig. 18) has a transition area (MA; Fig. 18) adjacent to the first display area (CA; Fig. 18), and the driving circuit (PC2; Fig. 18) is in the transition area (M; Fig. 18),
wherein the display substrate (1000; Fig. 13) further comprises at least one transparent wiring layer (TWL; Fig. 13; Paragraph [0240]; wherein discloses “The connection line TWL may include a transparent conductive material”) between the driving circuit (PC2; Fig. 13) and the anode of the light-emitting device (DE2; Fig. 13), and the driving circuit (PC2; Fig. 13) and the anode (DE2; Fig. 13) are electrically connected via a transparent wire in the transparent wiring layer (TWL; Fig. 13; Paragraph [0240]; wherein discloses “The connection line TWL may include a transparent conductive material”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cha in view of Kim and Jun’s display apparatus by applying driving circuit, as taught by An, so to use a display apparatus with driving circuit for improving the display quality of a display apparatus having plural display areas having different image resolution capabilities (Paragraph [0006]).
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Cha et al (US 2021/0359073 A1), Kim et al (US 2020/0118490 A1), Chen (US 2022/0310731 A1), Jun et al (US 2014/0118409 A1), and An et al (US 2022/0366847 A1) have been used for new ground rejection.
Claim 1 is rejected in view of newly discovered reference(s) to Kim et al (US 2020/0118490 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 08/21/2026
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