CTNF 19/293,151 CTNF 88133 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA 1. Claim s 1-7, 9-11, and 15-16 rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 3, 5, 13-14, 16 and 18-19 of U.S. Patent No. 12,424,176 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other because 19/293,151 (claim 1) 12,424,176 B2 (claim 1) A driving circuit, comprising a first driving signal generation circuit, a first output control circuit, a first gating circuit and a first output circuit; wherein N is a positive integer; A driving circuit, comprising a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; wherein N is a positive integer; the first driving signal generation circuit is electrically connected to a first first control node, a first second control node and an Nth stage of driving signal output terminal respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first first control node and a potential of the first second control node; the first driving signal generation circuit is electrically connected to a first first control node, a first second control node and an Nth stage of driving signal output terminal respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first first control node and a potential of the first second control node; the first output control circuit is electrically connected to a first first node, the first first control node and a first second node respectively, and is configured to control to connect the first first control node and the first second node under the control of a potential of the first first node; the first output control circuit is electrically connected to a first first node, the first first control node and a first second node respectively, and is configured to control to connect the first first control node and the first second node under the control of a potential of the first first node; the first gating circuit is electrically connected to the first first node, a gating input terminal and a gating control terminal respectively, and is configured to control to write a gating input signal provided by the gating input terminal into the first first node under the control of a gating control signal provided by the gating control terminal; the first gating circuit is electrically connected to the first first node, a gating input terminal and a gating control terminal respectively, and is configured to control to write a gating input signal provided by the gating input terminal into the first first node under the control of a gating control signal provided by the gating control terminal; the first first energy storage circuit is electrically connected to the first first node and the first second node respectively, and is configured to control a potential of the first second node according to the potential of the first first node; the first second energy storage circuit is electrically connected to a first third control node and an Nth stage of output driving terminal respectively, and is configured to control a potential of the first third control node according to an Nth stage of driving output signal provided by the Nth stage of output driving terminal; the first output circuit is electrically connected to the first second node, a control electrode, a first voltage terminal, a second voltage terminal and the Nth stage of output driving terminal respectively, and is configured to control the connection between the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and control the connection between the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the control electrode. the first output circuit is electrically connected to the first second node, the first third control node, a first voltage terminal, a second voltage terminal and the Nth stage of output driving terminal respectively, and is configured to control the connection between the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and control the connection between the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node; the first third control node and the first second control node are different nodes. 19/293,151 (claim 2) 12,424,176 B2 (claim 3) The driving circuit according to claim 1, wherein the first gating circuit includes a first first transistor; a gate electrode of the first first transistor is electrically connected to the gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to the gating input terminal. The driving circuit according to claim 1, wherein the first gating circuit includes a first first transistor; a gate electrode of the first first transistor is electrically connected to the gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to the gating input terminal. 19/293,151 (claim 3) 12,424,176 B2 (claim 5) The driving circuit according to claim 1, wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node. The driving circuit according to claim 1, wherein the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor; a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage of output driving terminal; or wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the Nth stage of output driving terminal, the first second node and the first voltage terminal respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage of driving output signal provided by the Nth stage of output driving terminal; wherein the first second node control circuit comprises a first fourth transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein the first second node control circuit comprises a first fourth transistor and a first control transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; and a gate electrode of the first control transistor is electrically connected to the Nth stage of output driving terminal, and a first electrode of the first control transistor is electrically connected to the first second node. 19/293,151 (claim 4) 12,424,176 B2 (claim 5) The driving circuit according to claim 2, wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node. The driving circuit according to claim 1, wherein the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor; a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage of output driving terminal; or wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the Nth stage of output driving terminal, the first second node and the first voltage terminal respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage of driving output signal provided by the Nth stage of output driving terminal; wherein the first second node control circuit comprises a first fourth transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein the first second node control circuit comprises a first fourth transistor and a first control transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; and a gate electrode of the first control transistor is electrically connected to the Nth stage of output driving terminal, and a first electrode of the first control transistor is electrically connected to the first second node. 19/293,151 (claim 5) 12,424,176 B2 (claim 5) The driving circuit according to claim 1, further comprising a first second node control circuit; wherein the first second node control circuit is electrically connected to the control electrode, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the control electrode. The driving circuit according to claim 1, wherein the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor; a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage of output driving terminal; or wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the Nth stage of output driving terminal, the first second node and the first voltage terminal respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage of driving output signal provided by the Nth stage of output driving terminal; wherein the first second node control circuit comprises a first fourth transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein the first second node control circuit comprises a first fourth transistor and a first control transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; and a gate electrode of the first control transistor is electrically connected to the Nth stage of output driving terminal, and a first electrode of the first control transistor is electrically connected to the first second node. 19/293,151 (claim 6) 12,424,176 B2 (claim 5) The driving circuit according to claim 2, further comprising a first second node control circuit; wherein the first second node control circuit is electrically connected to the control electrode, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the control electrode. The driving circuit according to claim 1, wherein the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor; a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage of output driving terminal; or wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the Nth stage of output driving terminal, the first second node and the first voltage terminal respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage of driving output signal provided by the Nth stage of output driving terminal; wherein the first second node control circuit comprises a first fourth transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein the first second node control circuit comprises a first fourth transistor and a first control transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; and a gate electrode of the first control transistor is electrically connected to the Nth stage of output driving terminal, and a first electrode of the first control transistor is electrically connected to the first second node. 19/293,151 (claim 7) 12,424,176 B2 (claim 5) The driving circuit according to claim 5, wherein the first second node control circuit comprises a first fourth transistor; a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal. The driving circuit according to claim 1, wherein the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor; a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage of output driving terminal; or wherein the first output control circuit includes a first third transistor; a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node; or the driving circuit further includes a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the Nth stage of output driving terminal, the first second node and the first voltage terminal respectively, and is configured to control the connection between the first second node and the first voltage terminal under the control of the potential of the first third control node and the Nth stage of driving output signal provided by the Nth stage of output driving terminal; wherein the first second node control circuit comprises a first fourth transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein the first second node control circuit comprises a first fourth transistor and a first control transistor; a gate electrode of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; and a gate electrode of the first control transistor is electrically connected to the Nth stage of output driving terminal, and a first electrode of the first control transistor is electrically connected to the first second node. 19/293,151 (claim 9) 12,424,176 B2 (claim 13) The driving circuit according to claim 1, wherein the first driving signal generation circuit includes a first first driving output circuit, a first second driving output circuit, a first first control node control circuit and a first second control node control circuit; the first first control node control circuit is configured to control the potential of the first control node; the first second control node control circuit is configured to control the potential of the second control node; the first first driving output circuit is electrically connected to the first first control node, the first voltage terminal and the Nth stage of driving signal output terminal respectively, and is configured to control the connection between the Nth stage of driving signal output terminal and the first voltage terminal under the control of the potential of the first first control node; the first second driving output circuit is electrically connected to the first second control node, the second voltage terminal and the Nth stage of driving signal output terminal respectively, and is configured to control the connection between the Nth stage of driving signal output terminal and the second voltage terminal under the control of the potential of the first second control node. The driving circuit according to claim 1, wherein the first driving signal generation circuit includes a first first driving output circuit, a first second driving output circuit, a first first control node control circuit and a first second control node control circuit; the first first control node control circuit is configured to control the potential of the first control node; the first second control node control circuit is configured to control the potential of the second control node; the first first driving output circuit is electrically connected to the first first control node, the first voltage terminal and the Nth stage of driving signal output terminal respectively, and is configured to control the connection between the Nth stage of driving signal output terminal and the first voltage terminal under the control of the potential of the first first control node; the first second driving output circuit is electrically connected to the first second control node, the second voltage terminal and the Nth stage of driving signal output terminal respectively, and is configured to control the connection between the Nth stage of driving signal output terminal and the second voltage terminal under the control of the potential of the first second control node. 19/293,151 (claim 10) 12,424,176 B2 (claim 14) The driving circuit according to claim 9, wherein the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit and a first first control circuit; the first seventh node control circuit is electrically connected to a first seventh node, the second voltage terminal, a first clock signal terminal and a first fifth node respectively, and is configured to control the connection between the first seventh node and the second voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of a potential of the first fifth node; the first eighth node control circuit is electrically connected to the second voltage terminal, a first seventh node and a first eighth node respectively, and is configured to control the connection between the first seventh node and the first eighth node under the control of the second voltage signal provided by the second voltage terminal; the first third node control circuit is electrically connected to the first eighth node, a second clock signal terminal and the first third node respectively, and is configured to control the first third node to be electrically connected to the second clock signal terminal under the control of a potential of the first eighth node, and control the potential of the first third node according to the potential of the first eighth node; the first first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node and the first voltage terminal respectively, and is configured to control the first third node to be connected to the first first control node under the control of a second clock signal provided by the second clock signal terminal, and control the first first control node to be connected to the first voltage terminal under the control of the potential of the first fifth node. The driving circuit according to claim 13, wherein the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit and a first first control circuit; the first seventh node control circuit is electrically connected to a first seventh node, the second voltage terminal, a first clock signal terminal and a first fifth node respectively, and is configured to control the connection between the first seventh node and the second voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of a potential of the first fifth node; the first eighth node control circuit is electrically connected to the second voltage terminal, a first seventh node and a first eighth node respectively, and is configured to control the connection between the first seventh node and the first eighth node under the control of the second voltage signal provided by the second voltage terminal; the first third node control circuit is electrically connected to the first eighth node, a second clock signal terminal and the first third node respectively, and is configured to control the first third node to be electrically connected to the second clock signal terminal under the control of a potential of the first eighth node, and control the potential of the first third node according to the potential of the first eighth node; the first first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node and the first voltage terminal respectively, and is configured to control the first third node to be connected to the first first control node under the control of a second clock signal provided by the second clock signal terminal, and control the first first control node to be connected to the first voltage terminal under the control of the potential of the first fifth node. 19/293,151 (claim 11) 12,424,176 B2 (claim 16) The driving circuit according to claim 9, wherein the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit and a first second control circuit; the first sixth node control circuit is electrically connected to the second voltage terminal, the first ninth node, the first sixth node and the first fourth node respectively, and is configured to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and control the potential of the first sixth node according to the potential of the first fourth node; the first fifth node control circuit is electrically connected to the (N-1)th stage of driving signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal and the first voltage terminal respectively, and is configured to control the connection between the first fifth node and the (N-1)th stage of driving signal output terminal under the control of the first clock signal provided by the first clock signal terminal, and control the first fifth node to be connected to the first voltage terminal; the first ninth node control circuit is electrically connected to the first clock signal terminal, the (N-1)th stage of driving signal output terminal and the first ninth node respectively, and is configured to control the connection between the first ninth node and the (N-1)th stage of driving signal output terminal under the control of the first clock signal provided by the first clock signal terminal; the first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal and the first sixth node respectively, and is configured to control the connection between the first fourth node and the first voltage terminal under the control of the potential of the first seventh node, and control the connection between the first fourth node and the second clock signal terminal under the control of the potential of the first sixth node; the first second control circuit is electrically connected to the second voltage terminal, the first fifth node and the first second control node respectively, and is configured to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal. The driving circuit according to claim 13, wherein the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit and a first second control circuit; the first sixth node control circuit is electrically connected to the second voltage terminal, the first ninth node, the first sixth node and the first fourth node respectively, and is configured to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and control the potential of the first sixth node according to the potential of the first fourth node; the first fifth node control circuit is electrically connected to the (N-1)th stage of driving signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal and the first voltage terminal respectively, and is configured to control the connection between the first fifth node and the (N-1)th stage of driving signal output terminal under the control of the first clock signal provided by the first clock signal terminal, and control the first fifth node to be connected to the first voltage terminal; the first ninth node control circuit is electrically connected to the first clock signal terminal, the (N-1)th stage of driving signal output terminal and the first ninth node respectively, and is configured to control the connection between the first ninth node and the (N-1)th stage of driving signal output terminal under the control of the first clock signal provided by the first clock signal terminal; the first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal and the first sixth node respectively, and is configured to control the connection between the first fourth node and the first voltage terminal under the control of the potential of the first seventh node, and control the connection between the first fourth node and the second clock signal terminal under the control of the potential of the first sixth node; the first second control circuit is electrically connected to the second voltage terminal, the first fifth node and the first second control node respectively, and is configured to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal. 19/293,151 (claim 15) 12,424,176 B2 (claim 18) A driving method, applied to the driving circuit according to claim 1, comprising: generating and outputting, by the first driving signal generation circuit, the Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of the potential of the first first control node and the potential of the first second control node; controlling, by the first output control circuit, the connection between the first first control node and the first second node under the control of the potential of the first first node; controlling, by the first gating circuit, the gating input signal to be written into the first first node under the control of the gating control signal; controlling, by the first output circuit, the connection between the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and controlling the connection between the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the control electrode; wherein N is a positive integer. A driving method, applied to the driving circuit according claim 1, comprising: generating and outputting, by the first driving signal generation circuit, the Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of the potential of the first first control node and the potential of the first second control node; controlling, by the first output control circuit, the connection between the first first control node and the first second node under the control of the potential of the first first node; controlling, by the first gating circuit, the gating input signal to be written into the first first node under the control of the gating control signal; controlling, by the first first energy storage circuit, the potential of the first second node according to the potential of the first first node; controlling, by the first second energy storage circuit, the potential of the first third control node according to the Nth stage of driving output signal provided by the Nth stage of output driving terminal; controlling, by the first output circuit, the connection between the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and controlling the connection between the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node; wherein the first third control node and the first second control node are different nodes, and N is a positive integer. 19/293,151 (claim 16) 12,424,176 B2 (claim 19) A driving module, comprising a plurality of driving circuits according to claim 1; wherein an Nth driving circuit is electrically connected to the driving signal output terminal of an (N-1)th driving circuit; N is a positive integer. A driving module, comprising a plurality of driving circuits according to claim 1; wherein an Nth driving circuit is electrically connected to the driving signal output terminal of an (N-1)th driving circuit; N is a positive integer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMEN W BOGALE/Examiner, Art Unit 2628 /NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628 Application/Control Number: 19/293,151 Page 2 Art Unit: 2628 Application/Control Number: 19/293,151 Page 3 Art Unit: 2628 Application/Control Number: 19/293,151 Page 4 Art Unit: 2628 Application/Control Number: 19/293,151 Page 5 Art Unit: 2628 Application/Control Number: 19/293,151 Page 6 Art Unit: 2628 Application/Control Number: 19/293,151 Page 7 Art Unit: 2628 Application/Control Number: 19/293,151 Page 8 Art Unit: 2628 Application/Control Number: 19/293,151 Page 9 Art Unit: 2628 Application/Control Number: 19/293,151 Page 10 Art Unit: 2628 Application/Control Number: 19/293,151 Page 11 Art Unit: 2628 Application/Control Number: 19/293,151 Page 12 Art Unit: 2628 Application/Control Number: 19/293,151 Page 13 Art Unit: 2628 Application/Control Number: 19/293,151 Page 14 Art Unit: 2628 Application/Control Number: 19/293,151 Page 15 Art Unit: 2628 Application/Control Number: 19/293,151 Page 16 Art Unit: 2628 Application/Control Number: 19/293,151 Page 17 Art Unit: 2628 Application/Control Number: 19/293,151 Page 18 Art Unit: 2628 Application/Control Number: 19/293,151 Page 19 Art Unit: 2628 Application/Control Number: 19/293,151 Page 20 Art Unit: 2628 Application/Control Number: 19/293,151 Page 21 Art Unit: 2628 Application/Control Number: 19/293,151 Page 22 Art Unit: 2628 Application/Control Number: 19/293,151 Page 23 Art Unit: 2628 Application/Control Number: 19/293,151 Page 24 Art Unit: 2628 Application/Control Number: 19/293,151 Page 25 Art Unit: 2628 Application/Control Number: 19/293,151 Page 26 Art Unit: 2628 Application/Control Number: 19/293,151 Page 27 Art Unit: 2628 Application/Control Number: 19/293,151 Page 28 Art Unit: 2628 Application/Control Number: 19/293,151 Page 29 Art Unit: 2628 Application/Control Number: 19/293,151 Page 30 Art Unit: 2628 Application/Control Number: 19/293,151 Page 31 Art Unit: 2628 Application/Control Number: 19/293,151 Page 32 Art Unit: 2628 Application/Control Number: 19/293,151 Page 33 Art Unit: 2628 Application/Control Number: 19/293,151 Page 34 Art Unit: 2628 Application/Control Number: 19/293,151 Page 35 Art Unit: 2628 Application/Control Number: 19/293,151 Page 36 Art Unit: 2628 Application/Control Number: 19/293,151 Page 37 Art Unit: 2628 Application/Control Number: 19/293,151 Page 38 Art Unit: 2628 Application/Control Number: 19/293,151 Page 39 Art Unit: 2628 Application/Control Number: 19/293,151 Page 40 Art Unit: 2628 Application/Control Number: 19/293,151 Page 41 Art Unit: 2628 Application/Control Number: 19/293,151 Page 42 Art Unit: 2628 Application/Control Number: 19/293,151 Page 43 Art Unit: 2628 Application/Control Number: 19/293,151 Page 44 Art Unit: 2628 Application/Control Number: 19/293,151 Page 45 Art Unit: 2628 Application/Control Number: 19/293,151 Page 46 Art Unit: 2628 Application/Control Number: 19/293,151 Page 47 Art Unit: 2628 Application/Control Number: 19/293,151 Page 48 Art Unit: 2628 Application/Control Number: 19/293,151 Page 49 Art Unit: 2628 Application/Control Number: 19/293,151 Page 50 Art Unit: 2628 Application/Control Number: 19/293,151 Page 51 Art Unit: 2628 Application/Control Number: 19/293,151 Page 52 Art Unit: 2628 Application/Control Number: 19/293,151 Page 53 Art Unit: 2628
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