Prosecution Insights
Last updated: July 17, 2026
Application No. 19/293,637

Stack-Type Isotope Battery

Non-Final OA §103
Filed
Aug 07, 2025
Priority
Jul 22, 2024 — RE 10-2024-0096587 +2 more
Examiner
HILTON, ALBERT MICHAEL
Art Unit
1723
Tech Center
1700 — Chemical & Materials Engineering
Assignee
LG Energy Solution Ltd.
OA Round
1 (Non-Final)
61%
Grant Probability
Moderate
1-2
OA Rounds
2y 6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 61% of resolved cases
61%
Career Allowance Rate
113 granted / 184 resolved
-3.6% vs TC avg
Strong +43% interview lift
Without
With
+42.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
27 currently pending
Career history
218
Total Applications
across all art units

Statute-Specific Performance

§103
93.4%
+53.4% vs TC avg
§102
3.4%
-36.6% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 184 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species 1B in the reply filed on 22 May 2026 is acknowledged. However, Applicant has not provided a ground for traversing the restriction requirement between Species 1A and Species 1B. The requirement is still deemed proper and is therefore made FINAL. Applicant's election with traverse of Species 2A in the reply filed on 22 May 2026 is acknowledged. The traversal is on the ground(s) that interchanging n-type and p-type semiconductor materials is a well-known variation in semiconductor device design. This argument is considered to be persuasive, and the restriction requirement between Species 2A and Species 2B is withdrawn. Claims 1-4, 6-9, 11-20 are pending, claims 5 and 10 are withdrawn. Claim Objections Claims 1-4, 6-9, 11-20 are objected to because of the following informalities: Regarding claim 1, the phrase “which provides the first, second and third bodies respectively embedded in the first, second and third semiconductor layers are interconnected along the thickness direction” appears to have been intended to read “such that the first, second and third bodies respectively embedded in the first, second and third semiconductor layers are interconnected along the thickness direction.” Claims 2-4, 6-9, 11-20 are similarly objected to as the depend form claim 1. Appropriate correction is required. Also regarding claim 1, the phrase “which provides the first type of semiconductor material surrounding the first, second and third bodies embedded respectively in the first, second and third semiconductor layers are interconnected along the thickness direction” appears to have been intended to read “such that the first type of semiconductor material surrounding the first, second and third bodies embedded respectively in the first, second and third semiconductor layers are interconnected along the thickness direction” Claims 2-4, 6-9, 11-20 are similarly objected to as the depend form claim 1. Appropriate correction is required. Regarding claim 3, the phrase “which provides the first, second and third bodies respectively embedded in the first, second and third semiconductor layers are interconnected along the thickness direction” appears to have been intended to read “such that the first, second and third bodies respectively embedded in the first, second and third semiconductor layers are interconnected along the thickness direction.” Appropriate correction is required. Regarding claim 4, the phrase “which provides the first type of semiconductor material surrounding the first, second and third bodies embedded respectively in the first, second and third semiconductor layers are interconnected along the thickness direction” appears to have been intended to read “such that the first type of semiconductor material surrounding the first, second and third bodies embedded respectively in the first, second and third semiconductor layers are interconnected along the thickness direction” Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-4, 6-9, 12-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR 20220014734A, as read via machine translation), San et al. (CN 111446019A, as read via machine translation). As to claim 1, Lee et al. discloses a battery apparatus comprising: a semiconductor layer (see e.g. substrate 10, formed of a semiconductor, Lee et al.: [0048]-[0049] and Fig. 10); and a radioactive material embedded in at least part of the semiconductor layer (see e.g. radioactive isotope 70, Lee et al.: [0048] and Fig. 10) and configured to emit beta rays into the at least part of the semiconductor layers (see e.g. [0002], the isotope emits beta rays), wherein the semiconductor layer comprises a first semiconductor layer (see e.g. substrate 10, Lee et al.: Fig. 10). wherein a plurality of bodies of the radioactive material is embedded in the first semiconductor layer (see e.g. Lee et al.: Fig. 10, radioactive isotopes 70 read on a plurality of bodies and are embedded in addition area 20, which reads on a first semiconductor layer): such that, in the first semiconductor layer, each of the plurality of bodies extends along a thickness direction of the first semiconductor layer (see e.g. Lee et al.: Fig. 10, radioactive isotope 70 extends along the vertical direction), such that, in the first semiconductor layer, each of the plurality of bodies is distanced from adjacent bodies of the plurality of bodies in a plane perpendicular to the thickness direction (see e.g. Lee et al.: Fig. 10, radioactive isotopes 70 are spaced apart laterally), such that, in first semiconductor layer, each of the plurality of bodies is surrounded by a first type of semiconductor material (see e.g. addition region 20, which is a p-type semiconductor, Lee et al.: [0067] and Fig. 10) which is further surrounded by a second type of semiconductor material (see e.g. substrate 10, which is an n-type semiconductor, Lee et al.: [0066] and Fig. 10). Lee et al. only discloses a single first semiconductor layer, and does not disclose additional second and third semiconductor layers as required by claim 1. Additionally, Lee et al. does not disclose the claimed connections between the plurality of bodies. San et al., also working in the field of isotope battery systems, teaches an analogous isotope battery structure comprising a layer that contains a plurality of radioactive material bodies (see e.g. titanium dioxide nanotube array, San et al.: [0022] and Fig. 2). San et al. further teaches an arrangement in which a second layer is disposed above a first layer (see e.g. San et al.: Fig. 3). San et al.’s first and second layers have electrical contacts that are connected in parallel such that terminals of one polarity are connected together (see e.g. bottom electrodes 4 are connected together, San et al.: Fig: 3) and the terminals of the opposite polarity are connected together (see e.g. top electrode 1, San et al.; Fig: 3). San et al. further teaches that connecting the isotope batteries in this manner allows them to be connected in parallel as part of a series-parallel hybrid structure, and thereby deliver greater output power to an external load (see e.g. San et al.: [0037], Fig. 3). It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the battery apparatus of Lee et al. by: a) disposing an additional second layer above the first layer and a third layer above the second layer and b) connecting the positive and negative contacts together to connect the three layers in parallel in the manner suggested by San et al.. Illustration 1 below is a representation of this proposed modification. Said artisan would have been motivated to modify Lee et al.’s battery apparatus in this way in order to connect multiple layers together in a series-parallel hybrid structure and thereby deliver greater output power to an external load, as taught by San et al.. The proposed combination of Lee et al. with San et al. as shown in Illustration 1 yields a battery apparatus in which: a plurality of semiconductor layers generally parallel to one another (see e.g. Layers 1, 2, and 3 of Illustration 1) a radioactive material embedded in at least part of the plurality of semiconductor layers (see e.g. radioactive isotope 70, Lee et al.: [0048] and Fig. 10) and configured to emit beta rays into the at least part of the plurality of semiconductor layers (see e.g. [0002], the isotope emits beta rays), wherein the plurality of semiconductor layers comprises a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer (see e.g. Layers 3, 2, and 1, Illustration 1), wherein a plurality of bodies of the radioactive material is embedded in each of the first, second and third semiconductor layers (see e.g. Lee et al.: Fig. 10, substrate 10 comprises multiple bodies of radioactive isotope 70 embedded in the substrates): such that, in each of the first, second and third semiconductor layers, each of the plurality of bodies extends along a thickness direction of the first semiconductor layer (see e.g. Illustration 1, all of the bodies extend along the vertical direction), such that, in each of the first, second and third semiconductor layers, each of the plurality of bodies is distanced from adjacent bodies of the plurality of bodies in a plane perpendicular to the thickness direction (see e.g. Illustration 1, all of the isotope bodies are laterally spaced from each other), such that, in first, second and third semiconductor layers, each of the plurality of bodies is surrounded by a first type of semiconductor material (see e.g. addition region 20, which is a p-type semiconductor and surrounds each of the radioactive isotopes 70, Lee et al.: [0067] and Fig. 10) which is further surrounded by a second type of semiconductor material (see e.g. substrate 10, which is an n-type semiconductor, Lee et al.: [0066] and Fig. 10), such that a second body of the plurality of bodies embedded in the second semiconductor layer is connected to a first body of the plurality of bodies embedded in the first semiconductor layer and is further connected to a third body of the plurality of bodies embedded in the third semiconductor layer (see e.g. Illustration 2 below, showing first, second, and third bodies all being electrically connected together), such that the first, second and third bodies respectively embedded in the first, second and third semiconductor layers are interconnected along the thickness direction (see e.g. Illustration 2, first, second, and third bodies can reasonably be considered to be interconnected along the vertical/thickness direction), such that the first type of semiconductor material surrounding the second body embedded in the second semiconductor layer (see e.g. addition region 20, Lee et al.: [0067] and Fig. 10) is connected to the first type of semiconductor material surrounding the first body embedded in the first semiconductor layer and is further connected to the first type of semiconductor material surrounding the third body embedded in the third semiconductor layer (see e.g. Illustration 2, showing the semiconductor materials surrounding the first, second, and third bodies all being electrically interconnected), such that the first type of semiconductor material surrounding the first, second and third bodies embedded respectively in the first, second and third semiconductor layers are interconnected along the thickness direction (see e.g. Illustration 2, showing the semiconductor materials surrounding the first, second, and third bodies all being electrically interconnected along the vertical/thickness direction). PNG media_image1.png 1160 1058 media_image1.png Greyscale Illustration 1: Reproduction with modification of Fig. 1 of Lee et al., showing the proposed modification in which three isotope batteries are connected in series. Dashed lines connect to one set of contacts and the solid lines connect to the contacts of opposite polarity. PNG media_image2.png 1154 1124 media_image2.png Greyscale Illustration 2: Reproduction with modification of Fig. 1 of Lee et al., showing the first, second, and third bodies. As to claim 2, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first body embedded in the first semiconductor layer, the second body embedded in the second semiconductor layer, and the third layer embedded in the third semiconductor layer are aligned along the thickness direction (see e.g. Illustration 2, showing the first, second, and third bodies in respective first, second, and third layers all aligned along the vertical/thickness direction). As to claim 3, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the second body embedded in the second semiconductor layer contacts the first body embedded in the first semiconductor layer and further contacts the third body embedded in the third semiconductor layer, such that the first, second and third bodies respectively embedded in the first, second and third semiconductor layers are interconnected along the thickness direction (see e.g. Illustration 2, showing the first, second, and third bodies in respective first, second, and third layers all in electrical contact with each other such that they are interconnected along the vertical/thickness direction). As to claim 4, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first type of semiconductor material surrounding the second body (see e.g. addition region 20, which reads on the claimed first type of semiconductor material, Lee et al.: [0067] and Fig. 10) embedded in the second semiconductor layer contacts the first type of semiconductor material surrounding the first body embedded in the first semiconductor layer and further contacts the first type of semiconductor material surrounding the third body embedded in the third semiconductor layer (see e.g. Illustration 2, showing the semiconductor layers surrounding the first, second, and third bodies all being in electrical contact with each other), such that the first type of semiconductor material surrounding the first, second and third bodies embedded respectively in the first, second and third semiconductor layers are interconnected along the thickness direction (see e.g. Illustration 2, showing the semiconductor layers surrounding the first, second, and third bodies all being in electrical contact with each other and thereby being interconnected along the vertical/thickness direction). As to claim 6, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first semiconductor layer and the second semiconductor layer are distanced along the thickness direction (see e.g. Illustration 1, showing first and second layers distanced from each other along the vertical/thickness direction). As to claim 7, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first semiconductor layer and the second semiconductor layer have an intervening layer therebetween (see e.g. Illustrations 1 and 3, showing an intervening layer between each of the first, second, and third layers such that an intervening layer is between the first and second semiconductor layers). PNG media_image3.png 344 483 media_image3.png Greyscale Illustration 3: Reproduction with modification of Fig. 1 of Lee et al., showing the intervening layer. As to claim 8, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first semiconductor layer and the second semiconductor layer have a non-semiconductive intervening layer therebetween (see e.g. Lee et al.: Fig. and the intervening layer indicated in Illustration 3. Lee et al. does not explicitly state what this intervening layer is composed of or if it is non-semiconducting. However, Fig. 1 of Lee et al. depicts both this intervening layer and the insulating space charge region 30 as unshaded while all of the semiconducting and conducting elements are shaded with diagonal lines. Additionally, forming this intervening layer out of an insulating material would provide the benefit electrically isolate the semiconductor substate of the battery. As such, one of ordinary skill in the art prior to the filing date of the invention would have reasonably expected that this intervening layer is insulating and therefore non-semiconducting). As to claim 9, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first semiconductor layer and the second semiconductor layer are distanced in the thickness direction (see e.g. Illustration 1, the first and second layers are distanced from each other in the thickness/vertical direction), wherein the first body embedded in the first semiconductor layer, the second body embedded in the second semiconductor layer, and the third layer embedded in the third semiconductor layer are aligned along the thickness direction (see e.g. Illustration 2, showing the first, second, and third bodies in respective first, second, and third layers all aligned along the vertical/thickness direction). As to claim 12, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first type of semiconductor material comprises an N-type semiconductor material (see e.g. addition area 20, formed of a semiconductor that may be an n-type semiconductor, Lee et al.: [0066] and Fig. 10), wherein the second type of semiconductor material comprise a P-type semiconductor material (see e.g. addition region 20, which is doped to have the opposite polarity of substrate 10, and thereby is a p-type semiconductor when 10 is an n-type semiconductor, Lee et al.: [0066], Fig. 10). As to claim 13, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first type of semiconductor material comprises a P-type semiconductor material (see e.g. addition area 20, formed of a semiconductor that may be a p-type semiconductor, Lee et al.: [0066] and Fig. 10), wherein the second type of semiconductor material comprise an N-type semiconductor material (see e.g. addition region 20, which is doped to have the opposite polarity of substrate 10, and thereby is an n-type semiconductor when 10 is a pn-type semiconductor, Lee et al.: [0066], Fig. 10). As to claim 14, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the plurality of bodies in the first semiconductor layer passes through the first semiconductor layer along the thickness direction (see e.g. Lee et al.: Fig. 1, showing a plurality of bodies 70 that pass at least partially through addition region 20). As to claim 15, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the plurality of bodies is provided in through- holes extending along the thickness direction through the first type of semiconductor layer (see e.g. Lee et al.: Figs. 1 and 4, showing a plurality of bodies 70 that are provided in trenches 100 which read on through-holes and that pass at least partially through addition region 20). As to claim 18, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein, when viewed in the thickness direction, the plurality of bodies layer (see e.g. radioactive isotope 70, Lee et al.: [0048] and Fig. 1) is regularly arranged in the first semiconductor layer such that gaps between two immediately neighboring ones of the plurality of bodies are generally the same (see e.g. Lee et al.: Fig. 1, radioactive isotopes 70 are regularly arranged in addition region 20, which reads on a first semiconductor region such that that gaps between two immediately neighboring ones of the plurality of bodies 70 are generally the same). As to claim 19, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the first type of semiconductor interconnected in the first, second and third semiconductor layers is electrically connected to a first electrode of the battery apparatus (see e.g. Lee et al.: Fig. 1, San et al.: Fig. 3, and Illustration 1 above. The first type of semiconductor material 20 is electrically connected to second electrode 42, which reads on a first electrode as per Lee et al.: [0071]-[0072] and Fig. 1. These first electrodes of the three semiconductor layers are all electrically interconnected together as shown in Illustration 1). As to claim 20, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the second type of semiconductor interconnected in the first, second and third semiconductor layers is electrically connected to a second electrode of the battery apparatus (see e.g. Lee et al.: Fig. 1, San et al.: Fig. 3, and Illustration 1 above. The second type of semiconductor material 10 is electrically connected to first electrode 41, which reads on a first electrode as per Lee et al.: [0179] and Fig. 1. These first electrodes of the three semiconductor layers are all electrically interconnected together as shown in Illustration 1). Claim(s) 11 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR 20220014734A), San et al. (CN 111446019A) as applied to claim 1 above, and further in view of Gadeken et al. (US 2008/0199736). As to claim 11, Lee et al. in view of San et al. teaches the apparatus of Claim 1, wherein the plurality of bodies embedded in the third semiconductor layer individually comprises a top portion and a bottom portion that is closer to the second semiconductor layer than the top portion (see e.g. the first, second, and third bodies indicated in Illustration 2, which each can reasonably be considered to comprise a top portion and a bottom portion). Lee et al. in view of San et al.’s plurality of bodies all have a straight column shape such that, in a cross-section taken by a plane parallel to the thickness direction, the top portion has the same width as the bottom portion (see e.g. Lee et al.: Fig. 1). Gadeken et al., also working in the field of isotope batteries, teaches an analogous isotope battery apparatus that comprises a plurality of bodies (see e.g. radioactive material 422, Gadeken et al.: [0057] and Fig. 4) deposited within vertical channels of a semiconductor substrate (see e.g. pores 304, Gadeken et al.: [0057] and Fig. 4) that are analogous to the structure of Lee et al. in view of San et al.’s apparatus. Gadeken et al. teaches an embodiment in which the channels have a straight columnar shape (see e.g. Gadeken et al.: Fig. 4), but also teaches an embodiment in which the channels have a shape wherein, in a cross-section taken by a plane parallel to the thickness direction, the top portion is wider than the bottom portion (see e.g. Gadeken et al.; [0057] and Fig. 3, the pores 304 have a rounded bottom shape such that a bottom portion is narrower than the top portion). It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the apparatus of Lee et al. in view of San et al. by designing the bodies such that, in a cross-section taken by a plane parallel to the thickness direction, the top portion is wider than the bottom portion in the manner suggested by Gadeken et al.. This is because Gadeken et al. teaches that such a cross-sectional shape is a known functional equivalent to a straight columnar shape, and the modification would fail to produce any new benefit that would not have been reasonably expected by one of ordinary skill in the art. As to claim 16, Lee et al. in view of San et al. teaches the apparatus of Claim 1, comprising a plurality of bodies in the first semiconductor layer (see e.g. radioactive isotopes 70, in addition region 20, Lee et al.: Fig 1). Lee et al. in view of San et al. does not depict the cross-sectional shape of the plurality of bodies, and does not explicitly show that the plurality of bodies each has a round shape in a first cross-section taken by a first imaginary plane that passes the first semiconductor layer and is perpendicular to the thickness direction. Gadeken et al., also working in the field of isotope batteries, teaches an analogous isotope battery apparatus that comprises a plurality of bodies (see e.g. radioactive material 422, Gadeken et al.: [0057] and Fig. 4) deposited within vertical channels of a semiconductor substrate (see e.g. pores 304, Gadeken et al.: [0057] and Fig. 4) that are analogous to the structure of Lee et al. in view of San et al.’s apparatus. Gadeken et al. teaches an embodiment in which the plurality of bodies each have a round shape in a first cross-section taken by a first imaginary plane that passes the first semiconductor layer and is perpendicular to the thickness direction (see e.g. Gadeken et al.: Fig. 6A, showing radioactive material 422, which reads on the plurality of bodies, having a round cross-sectional shape). It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the apparatus of Lee et al. in view of San et al. by designing the plurality of bodies such that each has a round shape in a first cross-section taken by a first imaginary plane that passes the first semiconductor layer and is perpendicular to the thickness direction in the manner suggested by Gadeken et al.. This is because Gadeken et al. teaches that such a round cross-sectional shape is a known design choice for the cross-sectional shape of the plurality of bodies, and the use of a round shape would fail to produce any new benefit that would not have been reasonably expected by one of ordinary skill in the art. As to claim 17, Lee et al. in view of San et al. and Gadeken et al. teaches the apparatus of Claim 16, wherein, in the first cross-section the first type of semiconductor material has an annular shape surrounding each of the plurality of bodies in the first semiconductor layer (see e.g. Gadeken et al.: [0056] and Figs. 4 and 6A, n-type region 410 reads on the first type of semiconductor material and has an annular shape that surrounds each of the plurality of bodies 422 in the first semiconductor layer), wherein the annular shape of the first type of semiconductor material is interposed between the radioactive material and the second type of semiconductor material (see e.g. Gadeken et al.: [0056] and Figs. 4 and 6A, n-type region 410 reads on the first type of semiconductor material and is interposed between radioactive material 422 which reads on a plurality of bodies and p-type region 408, which reads on the second type of semiconductor material). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Murashev et al. (CN 110494929A, as read via machine translation) and Frye et al. (US 2017/0221595) both teach related isotope battery structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT HILTON whose telephone number is (571)272-4068. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tong Guo can be reached at (571)-272-3066. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.M.H./Examiner, Art Unit 1723 /BACH T DINH/Primary Examiner, Art Unit 1726 06/08/2026
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Prosecution Timeline

Aug 07, 2025
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §103 (current)

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