Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
The IDS, filed 8/26/25, has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tam (US20100235590A1), in view of Manning (US20140250279A1).
As to claim 1, 15:
TAM discloses an apparatus (memory system 100 having memory banks containing arrays of DRAM cells; 0019-0020), and associated method of its operation (0019-0025, Fig. 1, 2, 7, 8; claims 9-16) comprising:
an array of memory cells, the array of memory cells comprising a plurality of banks (memory banks M0-M7 each containing DRAM cells; 0020, 0087-0088); and
a controller coupled to the array of memory cells (arbitration logic 214; 0029, 0093-0099; memory bank M0 having bank decoder logic blocks, arbitration logic 814, and memory array 220, with the input registers receiving signals through broadcast network 720 and providing them to the bank decoder logic; 0093-0095), the controller configured to:
receive a command (receipt of access requests by the bank-specific circuitry; in memory bank M0 latch read-control signals, write-control signals, and address values provided through broadcast network 720, and provide those contents to bank decoder logic blocks; 0095; resulting local enable signals being supplied to arbitration logic 814; 0097-0099); the command comprising instructions for performing one or more [logical] operations on data stored in the plurality of banks wherein the command is multicast to a subset of controllers of a plurality of controllers that includes the controller coupled to the array of memory cells (access requests to be simultaneously provided to selected memory banks, the selected memory banks are interpreted as a subset of all the banks; simultaneous access requests are processed in parallel within the selected memory banks; 0026; read/write enable signals provided to arbitration logic 814 which causes multiplexer and address decoder to initiate accesses to memory array 220; 0098-0099); and output the instructions to a set of compute components to perform the one or more [logical] operations using the data stored in the plurality of banks, wherein each compute component of the set of compute components is associated with a respective bank of the plurality of banks (Upon receiving a read/write control value having the second state, address decoder 215 initiates a read access to memory array 220, wherein the word stored at the location specified by the local address value is read from memory array 220 via the sense amplifiers present in sense amplifier/write driver circuit 230; 0054; perform read/write access to memory array; 0002, 0004, 0021-0023, 0052-0054).
TAM does not specifically teach the command being instructions for performing one or more logical operations on the data in the banks. It is known in the art to use functional units, such as arithmetic logic unit, floating point circuity, and combination logical circuit to perform logic operations on data in the memory. MANNING teaches performing logical operations using memory-resident data. MANNING teaches identifying AND, OR, NOT, NAND, NOR and XOR operations (0003), while teaches instructions generated by a controller or host processor and operands stored in a memory array (0004). MANNING further teaches sensing circuitry including a compute component coupled to an array of memory cells (0024) and the compute component performing logical operations using data from the array as input (0025). MANNING further teaches control circuitry coupled to the array, sense amplifier and/or compute component for controlling signals corresponding to logical operations (0038).
It would have been obvious to one of ordinary skills, at the time of the invention, to modify the multi-bank memory architecture of TAM to incorporate the compute components and logical-operation circuitry of MANNING into the respective memory banks. The modification would have predictably enabled the individual memory banks to perform logical operations on data stored therein while maintaining the independently controlled, parallel multi-bank architecture of TAM.
MANNING expressly identifies increased parallel processing capability associated with performing logical operations in memory (0011, 0035). Thus, a person of ordinary skill in the art, at the time of the invention, would have been motivated to associate the compute components with the respective memory banks of TAM so that commands distributed to selected banks could be executed locally and in parallel. Accordingly, the combination renders obvious an apparatus comprising a plurality of memory banks, bank-specific arbitration/control circuitry receiving a distributed command containing instructions for logical operations such as AND, OR, NOT, NOR and XOR, and compute components associated with the respective memory banks for performing the logical operations using data stored in the memory banks.
As to claim 2, 9,16:
TAM teaches the set of compute components are configured to perform the one or more logical operations in parallel (access requests are provided to selected memory banks and processed in parallel; 0026, 0028). MANNING also teaches performing logical operations in parallel using compute/sensing circuitry associated with the memory array (0035,0011).
As to claim 3, 10, 17:
TAM teaches a set of one or more registers configured to store the instructions, wherein the instructions are read from the set of one or more registers for performing the one or more logical operations (input and output registers provided for the ports; 0019, 0021; read control and address information are latched in registers and provided to broadcast network; 0024-0025; each bank contains input registers, bank identification registers and other registers, with the stored signals supplied to bank-decoder logic; 0029-0030).
As to claim 4, 11, 18:
MANNING teaches the instructions comprise processing-in-memory instructions and are associated with the one or more logical operations using the data, wherein the data comprises one or more operands (PIM device; 0005; logical operations performed on operands; 0003-0004, 0022).
As to claim 5, 12, 19:
MANNING teaches the one or more logical operations comprise addition operations, multiplication operations, or any combination thereof (logical operation comprise addition, subtraction, multiplication, and division on operands; 0003; NAND operations can be combined to perform addition and multiplication, among other functions; 0036).
As to claim 6, 13, 20:
MANNING teaches the controller is further configured to: store respective results of the one or more logical operations in one or more banks of the plurality of banks without transferring the respective results to circuitry external to the plurality of banks (result of NAND operation is stored in memory array; 0030, 0034; compute functions can be performed without transferring data out of the memory array ; 0011).
As to claim 7, 14:
TAM teaches the plurality of banks comprise dynamic random access memory (DRAM) cells (DRAM; 0006, 0020, 0023).
As to claim 8:
TAM teaches a system (memory system with memory banks; 0019-0020), comprising: a host (memory controller; 0019, 0021, 0025); a plurality of banks of memory cells (0016-0020), wherein each bank of the plurality of banks of memory cells is associated with circuitry (dedicated bank control and bank-specific arbitration logic; 0028-0029; bank-specific arbitration logic receives local enable signals and produces a select signal to control the bank's multiplexer; 0050-0051) configured to perform one or more [logical] operations (process access requests from controller; 0004, 0026, 0095-0099) using data stored in the plurality of banks of memory cells; and
one or more components coupled with the host and configured to generate a multicast command comprising instructions for performing the one or more [logical] operations, wherein the multicast command is output to a subset of controllers of a plurality of controllers associated with the plurality of banks of memory cells (access requests to be simultaneously provided to selected memory banks, the selected memory banks are interpreted as a subset of all the banks; simultaneous access requests are processed in parallel within the selected memory banks; 0026; read/write enable signals provided to arbitration logic 814 which causes multiplexer and address decoder to initiate accesses to memory array 220; 0098-0099; interpretation: ), wherein each controller of the subset of controllers is configured to: output the instructions to the circuitry configured to perform the one or more logical operations (Upon receiving a read/write control value having the second state, address decoder 215 initiates a read access to memory array 220, wherein the word stored at the location specified by the local address value is read from memory array 220 via the sense amplifiers present in sense amplifier/write driver circuit 230; 0054; perform read/write access to memory array; 0002, 0004, 0021-0023, 0052-0054).
TAM does not specifically teach the command being instructions for performing one or more logical operations on the data in the banks. It is known in the art to use functional units, such as arithmetic logic unit, floating point circuity, and combination logical circuit to perform logic operations on data in the memory. MANNING teaches performing logical operations using memory-resident data. MANNING teaches identifying AND, OR, NOT, NAND, NOR and XOR operations (0003), while teaches instructions generated by a controller or host processor and operands stored in a memory array (0004). MANNING further teaches sensing circuitry including a compute component coupled to an array of memory cells (0024) and the compute component performing logical operations using data from the array as input (0025). MANNING further teaches control circuitry coupled to the array, sense amplifier and/or compute component for controlling signals corresponding to logical operations (0038).
It would have been obvious to one of ordinary skills, at the time of the invention, to modify the multi-bank memory architecture of TAM to incorporate the compute components and logical-operation circuitry of MANNING into the respective memory banks. The modification would have predictably enabled the individual memory banks to perform logical operations on data stored therein while maintaining the independently controlled, parallel multi-bank architecture of TAM.
MANNING expressly identifies increased parallel processing capability associated with performing logical operations in memory (0011, 0035). Thus, a person of ordinary skill in the art, at the time of the invention, would have been motivated to associate the compute components with the respective memory banks of TAM so that commands distributed to selected banks could be executed locally and in parallel. Accordingly, the combination renders obvious an apparatus comprising a plurality of memory banks, bank-specific arbitration/control circuitry receiving a distributed command containing instructions for logical operations such as AND, OR, NOT, NOR and XOR, and compute components associated with the respective memory banks for performing the logical operations using data stored in the memory banks.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 7-9, and 14-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 6, and 11 of U.S. Patent No. US 12,393,342.
Claim(s) 1, 3, 6, and 11 of patent #12,393,342 contain(s) every element of claim(s) 1-2, 7-9, and 14-16 of the instant application and as such anticipate(s) claim(s) 1-2, 7-9, and 14-16 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
The following is an example claim mapping between the current application and patent:
Current Application
An apparatus, comprising:
an array of memory cells, the array of memory cells comprising a plurality of banks; and
a controller coupled to the array of memory cells, the controller configured to: receive a command comprising instructions for performing one or more logical operations on data stored in the plurality of banks, wherein the command is multicast to a subset of controllers of a plurality of controllers that includes the controller coupled to the array of memory cells; and
output the instructions to a set of compute components to perform the one or more logical operations using the data stored in the plurality of banks, wherein each compute component of the set of compute components is associated with a respective bank of the plurality of banks.
Patent 12,393,342
An apparatus, comprising:
an array of memory cells; and
a controller coupled to the array, the controller configured to: receive, via a component, a command comprising instructions for performing one or more logical operations on data within a plurality of banks of the array of memory cells in parallel, wherein the command is multicast to a subset of controllers of a plurality of controllers, the subset including the controller; and
send the instructions to one or more compute components each associated with respective banks of the plurality of banks to perform, in parallel, the one or more logical operations.
As can be seen above, claim 1 of patent 12,393,342 includes the limitations of claim 1 of the instant application, anticipating claim 1 of the instant application. The only difference is claim 1 uses the term “output the instructions” while the patent uses “send the instructions”. One of ordinary skills in the art, at the time of the invention, would readily recognize that these wordings are equivalents, both transmit instructions to the compute components.
Claims 2, 7-9, and 14-16 of the instant application is similarly mapped to claims 1, 3, 6, or 11 of the 12,393,342 patent.
Conclusion
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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