DETAILED ACTION
The instant application having Application No. 19/295,952 has a total of 20 claims pending in the application, there are 2 independent claims and 18 dependent claims, all of which are ready for examination by the examiner.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
As required by M.P.E.P. ' 201.14(c), acknowledgment is made of applicant's claim for priority based on an application JP2018-174120 filed in JAPAN on 09/18/2018.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant's drawings submitted 8/11/2025 are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 8/11/2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 12,417,025. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Instant Application
US 12,417,025
1. A information processing system comprising:a host system including: a main memory; and processor circuitry, and
a memory system connected with the host system via a bus, wherein the processor circuitry is configured to: generate one or more read commands each specifying a logical address; and transmit the one or more read commands to the memory system, and the memory system includes:
a nonvolatile memory including a memory cell array, an input/output buffer, and a plurality of intermediate buffers each electrically connected between the memory cell array and the input/output buffer, the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page, the plurality of intermediate buffers including at least a first intermediate buffer and a second intermediate buffer, the second intermediate buffer being different from the first intermediate buffer; and
a controller electrically connected to the nonvolatile memory and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page;
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first intermediate buffer, and designation of the first page, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; and
by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer.
1. A memory system comprising:
a nonvolatile memory including a memory cell array, an input/output buffer, and a plurality of intermediate buffers each electrically connected between the memory cell array and the input/output buffer, the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page, the plurality of intermediate buffers including at least a first intermediate buffer and a second intermediate buffer, the second intermediate buffer being different from the first intermediate buffer; and a controller electrically connected to the nonvolatile memory and configured to:
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first intermediate buffer, and designation of the first page, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; and
by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer.
It would have been obvious at the time the invention was filed to modify claim 1 of US 12,417,025 for the benefit of obtaining the invention as specified in claim 1 of the instant application, as the limitations not found in claim 1 of US 12,417,025 would be obvious to add to claim 1 of the instant application, as memory systems are frequently connected to host systems that send read and write commands.
The other independent claims correspond as follows:
Instant Application
US 12,417,025
Claim 11
Claim 11
Further, the dependent claims of both cases contain substantially similar limitations.
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 11,941,251. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Instant Application
US 11,941,251
1. A information processing system comprising:a host system including: a main memory; and processor circuitry, and
a memory system connected with the host system via a bus, wherein the processor circuitry is configured to: generate one or more read commands each specifying a logical address; and transmit the one or more read commands to the memory system, and the memory system includes:
a nonvolatile memory including a memory cell array, an input/output buffer, and a plurality of intermediate buffers each electrically connected between the memory cell array and the input/output buffer, the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page, the plurality of intermediate buffers including at least a first intermediate buffer and a second intermediate buffer, the second intermediate buffer being different from the first intermediate buffer; and
a controller electrically connected to the nonvolatile memory and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page;
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first intermediate buffer, and designation of the first page, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; and
by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer.
1. A method of controlling a nonvolatile memory, the nonvolatile memory including a memory cell array including a plurality of pages, an input/output buffer, and one or more intermediate buffers each electrically connected between the memory cell array and the input/output buffer, said method comprising:
storing, in a first intermediate buffer, data read through a sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a first sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers; and
storing, in the input/output buffer, data read through a sensing operation from a third page out of the plurality of pages in accordance with a third command that includes a third sensing operation instruction and does not include designation of any of the intermediate buffers, and outputting the data stored in the input/output buffer in accordance with a fourth command that includes an output instruction.
2. The method according to claim 1, wherein the one or more intermediate buffers further include a second intermediate buffer different from the first intermediate buffer, and the method further comprises: storing, in the second intermediate buffer, data read through a sensing operation from a second page out of the plurality of pages in accordance with a second command that includes a second sensing operation instruction and designation of the second intermediate buffer.
It would have been obvious at the time the invention was filed to modify claim 1 of US 12,417,025 for the benefit of obtaining the invention as specified in claim 1 of the instant application, as the limitations not found in claim 1 of US 11,941,251 would be obvious to add to claim 1 of the instant application, as memory systems are frequently connected to host systems that send read and write commands, and memory systems generally contain controllers for performing these commands.
Independent claim 11 is rejected under similar rationale.
Further, the dependent claims of both cases contain substantially similar limitations.
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 11,068,167. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Instant Application
US 11,068,167
1. A information processing system comprising:a host system including: a main memory; and processor circuitry, and
a memory system connected with the host system via a bus, wherein the processor circuitry is configured to: generate one or more read commands each specifying a logical address; and transmit the one or more read commands to the memory system, and the memory system includes:
a nonvolatile memory including a memory cell array, an input/output buffer, and a plurality of intermediate buffers each electrically connected between the memory cell array and the input/output buffer, the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page, the plurality of intermediate buffers including at least a first intermediate buffer and a second intermediate buffer, the second intermediate buffer being different from the first intermediate buffer; and
a controller electrically connected to the nonvolatile memory and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page;
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first intermediate buffer, and designation of the first page, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; and
by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer.
1. A nonvolatile memory comprising:
a memory cell array including a plurality of pages; an input/output buffer; one or more intermediate buffers each electrically connected between the memory cell array and the input/output buffer; and a control circuit configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers,
wherein the control circuit is further configured to store, in the input/output buffer, data read through sensing operation from a third page out of the plurality of pages in accordance with a third command that includes a sensing operation instruction and does not include designation of any of the intermediate buffers, and output the data stored in the input/output buffer in accordance with a fourth command that includes an output instruction.
2. The nonvolatile memory according to claim 1, wherein the one or more intermediate buffers further include a second intermediate buffer different from the first intermediate buffer, and the control circuit is further configured to store, in the second intermediate buffer, data read through sensing operation from a second page out of the plurality of pages in accordance with a second command that includes a sensing operation instruction and designation of the second intermediate buffer.
It would have been obvious at the time the invention was filed to modify claim 1 of US 12,417,025 for the benefit of obtaining the invention as specified in claim 1 of the instant application, as the limitations not found in claim 1 of US 11,068,167 would be obvious to add to claim 1 of the instant application, as memory systems are frequently connected to host systems that send read and write commands.
The other independent claims correspond as follows:
Instant Application
US 11,068,167
Claim 11
Claim 11
Further, the dependent claims of both cases contain substantially similar limitations.
ALLOWABLE SUBJECT MATTER
Regarding Claim 1, Shin, the closest prior art of record, teaches: a information processing system comprising:
a host system (host 2100 of Fig. 19) including:
a main memory (though not explicitly shown on Fig. 19, the examiner notes main memory in a host system is common in the art); and
processor circuitry (though not explicitly shown on Fig. 19, the examiner notes processor circuitry in a host system is common in the art), and
a memory system connected with the host system via a bus (memory system 2200 of Fig. 19), wherein the processor circuitry is configured to:
generate one or more read commands each specifying a logical address; and
transmit the one or more read commands to the memory system (read commands are generated, Paragraphs 0039-0040, and though a logical address is not explicitly taught, the examiner notes a host using a logical address is common in the art), and
the memory system includes:
a nonvolatile memory including a memory cell array (cell array 110 of Fig. 2, which is a NAND/nonvolatile memory, Paragraph 0031), an input/output buffer (Input/Output Buffer 140 of Fig. 1), and a plurality of intermediate buffers each electrically connected between the memory cell array and the input/output buffer (the intermediate buffers corresponding to the latches in the “Page Buffer” 130 of Fig. 1, which includes multiple page buffers PB1-PBN), the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page (cell array 110 uses pages, Paragraph 0033), the plurality of intermediate buffers including at least a first intermediate buffer and a second intermediate buffer, the second intermediate buffer being different from the first intermediate buffer (the intermediate buffers corresponding to the latches in the “Page Buffer” 130 of Fig. 1); and
a controller electrically connected to the nonvolatile memory (control logic 150 of Fig. 1) and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page (“Each of the plurality of page buffers PB1 to PBn may perform a latching operation for sensing and storing data of selected memory cells to perform an On-Chip Valley Search (OCVS) read operation,” Paragraph 0036).
However, the cited prior art does not teach or suggest:
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first intermediate buffer, and designation of the first page, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; and by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer.
The claim requires a command sequence (e.g., the command sequence on Figs. 5A-5D of the instant application) that contains a designation of the first intermediate buffer, and designation of the first page, to instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer and a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, to instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer. The designation of first and second intermediate buffers in a command sequence is not present in the cited prior art. Therefore, claim 1 contains allowable subject matter.
Therefore, claim 1 contains allowable subject matter.
Regarding Claim 11, Shin, the closest prior art of record, teaches: a information processing system comprising:
a host system (host 2100 of Fig. 19) including:
a main memory (though not explicitly shown on Fig. 19, the examiner notes main memory in a host system is common in the art); and
processor circuitry (though not explicitly shown on Fig. 19, the examiner notes processor circuitry in a host system is common in the art), and
a memory system connected with the host system via a bus (memory system 2200 of Fig. 19), wherein the processor circuitry is configured to:
generate one or more read commands each specifying a logical address; and
transmit the one or more read commands to the memory system (read commands are generated, Paragraphs 0039-0040, and though a logical address is not explicitly taught, the examiner notes a host using a logical address is common in the art), the memory system includes:
a nonvolatile memory including a memory cell array (cell array 110 of Fig. 2, which is a NAND/nonvolatile memory, Paragraph 0031), an input/output buffer (Input/Output Buffer 140 of Fig. 1), and one or more intermediate buffers each electrically connected between the memory cell array and the input/output buffer (the intermediate buffers corresponding to the latches in the “Page Buffer” 130 of Fig. 1, which includes multiple page buffers PB1-PBN), the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page (cell array 110 uses pages, Paragraph 0033), the one or more intermediate buffers including at least a first intermediate buffer (the intermediate buffers corresponding to the latches in the “Page Buffer” 130 of Fig. 1); and a controller electrically connected to the nonvolatile memory (control logic 150 of Fig. 1) and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page (“Each of the plurality of page buffers PB1 to PBn may perform a latching operation for sensing and storing data of selected memory cells to perform an On-Chip Valley Search (OCVS) read operation,” Paragraph 0036).
However, the cited prior art does not teach or suggest:
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first page, and designation of the first intermediate buffer, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second page, but does not include designation of any of the intermediate buffers, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the input/output buffer; by transmitting, to the nonvolatile memory, a third command sequence that includes an output instruction, instruct the nonvolatile memory to output the second data from the input/output buffer; and transmit the second data to the host system, and the processor circuitry of the host system is further configured to: store the second data, which has been received from the memory system, into the main memory.
The claim requires a first command sequence (e.g., the command sequence on Figs. 5A-5D of the instant application) that contains a designation of the first intermediate buffer, and a second command sequence that does not include designation of any of the intermediate buffers, to instruct the nonvolatile memory to store second data read through a sensing operation. This is not taught or suggested by the prior art of record. Therefore, claim 11 contains allowable subject matter.
The dependent claims contain allowable subject matter as they depend from a base claim with allowable subject matter.
The examiner notes there is an outstanding double patenting rejection for claims 1-20 as noted above.
CLOSING COMMENTS
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
Prosecution Insights