Prosecution Insights
Last updated: October 22, 2026
Application No. 19/296,402

QUANTIZATION EXTRACTION FOR PHASE-LOCKED LOOP OSCILLATORS

Non-Final OA §102§DOUBLEPATENT
Filed
Aug 11, 2025
Priority
Dec 22, 2023 — continuation of 12/388,449
Examiner
ALMO, KHAREEM E
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
640 granted / 732 resolved
+27.4% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
16 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
36.9%
-3.1% vs TC avg
§102
55.3%
+15.3% vs TC avg
§112
2.7%
-37.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 732 resolved cases

Office Action

§102 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12388449. Although the claims at issue are not identical, they are not patentably distinct from each other because Gunasekaran et al. US 12388449 discloses the same device in claims 1, 2, 4, 6, 8, 9 and 10. Claims 1, 4-6, and 9 being equivalent to claim 1 and 6, claims 2 and 3 being equivalent to claims 4, claims 4,8, 10, 14, 18 and 19 being equivalent to claim 2, claims 12 and 13 equivalent to claim 8, claims 14-18 equivalent to claim 9, claims 11 and 20 being equivalent to claim 10 respectively of Guansekaran et al. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 7 and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gupta et al. (US 11418200). PNG media_image1.png 658 679 media_image1.png Greyscale 11418200. With respect to claim 1, An electronic circuit comprising: a first phase frequency detector (PFD) (PFD) having first (CLKre(t)) and second inputs (CLKfb(t)), and an output (at U(t) or D(t)) ;an adder circuit (20 and current produced by 150, the current of the charge pump is added with the current produced by 150 due to Kirchoff’s Current Law) having a first input coupled to the output of the first PFD (i.e at U(t) or D(t)), and an output (Icp(t)’); an oscillator (VCO) having an input (Vctr(t)) coupled to the output of the adder circuit (coupled via 22); a first frequency divider (34) having an input coupled to an output of the oscillator, and an output coupled to the second input of the first PFD; and a quantization circuit (140, 130, 120 and 44) having a first input (at 120) coupled to the output of the oscillator, a second input (at 44) coupled to the output of the first frequency divider, and an output coupled to a second input of the adder circuit (at 144 or 142). With respect to claim 7, Gupta et al. discloses the electronic circuit of claim 1, wherein the quantization circuit comprises: a quantization extraction circuit (120) having an input coupled to the output of the oscillator (output of oscillator VCO, Vout(t) coupled to sync) ; and a second PFD (130 replica PFD) having a first input coupled to a first output of the quantization extraction circuit, and an output coupled (via 140) to the second input of the adder circuit. With respect to claim 14, Gupta et al. discloses electronic circuit of claim 1, wherein the quantization circuit comprises: a quantization extraction circuit (120) having an input coupled to the output of the oscillator; and a switching circuit (140) having a first input coupled (via 130) to a first output of the quantization extraction circuit, and an output (144 or 142) coupled to the second input of the adder circuit. PNG media_image2.png 367 599 media_image2.png Greyscale With respect to claim 15, Gupta et al. discloses the electronic circuit of claim 14, wherein the quantization extraction circuit (120) comprises: a first delay circuit (126) having an output (122) coupled (via 130) to the first input (i.e. Urep(t)) of the switching circuit; and a second delay circuit (128) having an output (124) coupled (via 140) to a second input (i.e. Drep(t)) of the switching circuit. Allowable Subject Matter Claims 2-6, 8-13 and 16-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 2, the prior art fails to suggest or disclose further comprising a charge pump having an input coupled to the output of the adder circuit, and an output coupled to the input of the oscillator. Claim 3 is allowable based on its dependence on claim 2. With respect to claim 4, the prior art fails to suggest or disclose further comprising a masking circuit having a first input coupled to the output of the first frequency divider, and an output coupled to the second input of the quantization circuit. Claims 5-6 are allowable based on their dependence on claim 4. With respect to claim 8, the prior art fails to suggest or disclose further comprising a switching circuit having a first input coupled (via 130) to the first output of the quantization extraction circuit, and a first output coupled to the first input of the second PFD. Claim 9-13 are allowable based on their dependence on claim 8. With respect to claim 16, the prior art fails to suggest or disclose further comprising: a first logic circuit having a first input coupled to the output of the first frequency divider; a second input coupled to the output of the first delay circuit, and an output coupled to the first input of the switching circuit; and a second logic circuit having a first input coupled to the output of the first frequency divider, a second input coupled to the output of the second delay circuit, and an output coupled to the second input of the switching circuit. Claim 17, is allowable based on its dependence on claim 16. With respect to claim 18, the prior art fails to suggest or disclose further comprising a masking circuit having a first input coupled to the output of the first frequency divider, and an output coupled to the switching circuit. Claims 19 and 20 are allowable based on their dependence on claim 18. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAREEM E ALMO/Examiner, Art Unit 2836 /Menatoallah Youssef/SPE, Art Unit 2836
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Prosecution Timeline

Aug 11, 2025
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §102, §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.8%)
2y 3m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 732 resolved cases by this examiner. Grant probability derived from career allowance rate.

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