Prosecution Insights
Last updated: October 26, 2026
Application No. 19/296,569

TECHNIQUES FOR FOUR CYCLE ACCESS COMMANDS

Non-Final OA §102
Filed
Aug 11, 2025
Priority
Apr 07, 2022 — provisional 63/328,503 +1 more
Examiner
YU, JAE UN
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
677 granted / 753 resolved
+34.9% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
13 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
5.3%
-34.7% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 753 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1, 6-13, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2019/0196961), “Li”. 2. As per claim 1, Li discloses receiving, over a command-address channel associated with a plurality of data channels, an access command [a processor accessing dies over plurality of channels, figure 8]; decoding, according to a command truth table [mapping information, abstract], the access command, wherein the command truth table indicates that the access command comprises an operation code that indicates a type of the access command [an operation instruction divided into a plurality of instructions, S203, figure 2A], a first address of a memory die targeted by the type of the access command, and a second address of the memory die targeted by the type of the access command [determining target dies according to the mapping information, S208, figure 2B]; communicating, in accordance with the access command, first data corresponding to the first address over a first data channel of the plurality of data channels; and communicating, in accordance with the access command, second data corresponding to the second address over a second data channel of the plurality of data channels [communicating with dies over plurality of channels, figure 8]. 3. As per claim 6, Li discloses wherein, in accordance with the command truth table, the operation code is received over a first unit interval of a plurality of unit intervals indicated in the command truth table, at least a portion of the first address is received over a second unit interval of the plurality of unit intervals, and at least a portion of the second address is received over a third unit interval of the plurality of unit intervals [processing commands/addresses over clock intervals, figure 3]. 4. As per claim 7, Li discloses wherein the command truth table indicates that the operation code, the at least the portion of the first address, and the at least the portion of the second address are received over one or more command-address pins [a plurality of pins, figure 4] of the command-address channel [communicating with dies over plurality of channels, figure 8] during a respective unit interval of the plurality of unit intervals [processing commands/addresses over clock intervals, figure 3]. 5. As per claim 8, Li discloses wherein the command truth table indicates a bit configuration of the access command [mapping information, abstract]. 6. As per claim 9, Li discloses wherein the bit configuration indicates a respective bit that is communicated over a respective command-address pin [a plurality of pins, figure 4] of the command-address channel [communicating with dies over plurality of channels, figure 8] during a respective cycle of the access command [processing commands/addresses over clock intervals, figure 3]. 7. As per claim 10, Li discloses wherein: a first pseudo-channel of the memory die comprises the first data channel and the command-address channel, and a second pseudo-channel of the memory die comprises the second data channel and the command-address channel [a plurality of channels, figure 8]. 8. As per claim 11, Li discloses wherein the command truth table indicates that a bit of the access command received over a unit interval of the access command [processing commands/addresses over clock intervals, figure 3] indicates that the operation code applies to both the first address and the second address [determining target dies according to the mapping information, S208, figure 2B]. 9. As per claim 12, Li discloses wherein communication of the first data over the first data channel and communication of the second data over the second data channel are initiated at a same time based at least in part on the operation code applying to both the first address and the second address [parallel execution, paragraph 8]. 10. As per claims 13 and 17-19, the examiner directs the applicant’s attention to claim rejection above. Conclusion A. Allowable Subject Matter Claims 2-5, 14-16, and 20 are objected to. The closest prior art of record, “Li” discloses access mapping in figure 2B. The primary reasons for allowance of claims 2, 14, and 20 in the instant application is the combination with the inclusion in these claims that “wherein decoding the access command comprises: determining, based at least in part on the command truth table, that a respective set of bits of one or more sets of bits of the access command corresponds to a respective unit interval of one or more unit intervals of the access command”. The prior art of record neither anticipates nor renders obvious the above recited combination. As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP. B. Claims Rejected Claims 1, 6-13, and 17-19 are rejected. C. Direction for Future Remarks Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAE U YU/Primary Examiner, Art Unit 2138
Read full office action

Prosecution Timeline

Aug 11, 2025
Application Filed
Oct 14, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12737136
MANAGEMENT OF OPERATING SYSTEM SOFTWARE USING READ-ONLY MULTI-ATTACH BLOCK VOLUMES
1y 8m to grant Granted Sep 15, 2026
Patent 12737286
INTERLEAVED MEMORY TRANSACTION TRACKING FOR TRANSACTIONS WITH UNRELATED LENGTHS
1y 6m to grant Granted Sep 15, 2026
Patent 12710901
IMPLEMENTING COHERENCY AND PAGE CACHE SUPPORT IN A DISTRIBUTED WAY FOR FILES
1y 6m to grant Granted Aug 18, 2026
Patent 12705182
PROCESSING CACHE EVICTIONS IN A DIRECTORY SNOOP FILTER WITH ECAM
1y 5m to grant Granted Aug 11, 2026
Patent 12699654
PACKET PROCESSING DEVICE TO DETERMINE MEMORY TO STORE DATA IN A SERVER ARCHITECTURE AND COMPUTING SYSTEM INCLUDING SAME
4y 1m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.7%)
2y 6m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 753 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month