Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-19 are pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20220171706 A1 (CHO et al) in view of US 20210026548 (KANG).
With respect to claim 1, CHO (US 20220171706 A1) teaches data storage device comprising: a storage medium; and a memory controller configured to control the storage medium
[operating method of a memory system featuring data processing operation with respect to a memory device in the memory system comprising memory controller that performs a command operation corresponding to a command received from host system (Fig. 1; Par. 0034-0039)], wherein the memory controller is configured to:
create a physical-logical address table (P2LT) with mapping information between a physical address of the storage medium and a logical address provided from an external device
(map management operation including determining that a map management operation is triggered, based on physical-to-logical (P2L) entries generated after a previous map management operation, the physical-to-logical (P2L) entry corresponding to a physical address of a target memory unit) [Abstract; Fig. 5; Par. 0068-0073; Par. 0036-0037],
read an update target logical-physical address (L2P) segment from a logical-physical address table (L2PT) stored on the storage medium based on the P2LT
[when a map management operation is triggered, indicating a map management operation, pre-update table that indicate pre-update statuses of L2P segments including L2P entries to be updated based on the P2L entries because of storing data in the target memory region until the current map management operation is triggered after the previous map management operation is completed (Par. 0046-0047)];
the L2P table includes state entries respectively corresponding to all logical-to-physical (L2P) segments and each of the states indicates whether a corresponding (pre-update) L2P segment includes an L2P entry correspond to a logical address included in the P2L entries) [Abstract; Fig. 5; Par. 0005-0007; Par. 0068-0073; Par. 0042-0044],
store an update target L2P entry from the update target L2P segment and update the physical address of the update target L2P entry whenever the update target L2P entry is stored
[L2P update to perform an L2P update operation for updating an L2P entry based on a P2L entry to keep the L2P entry up-to-date (Par. 0042-0043; Par. 0005-0007)
controller to perform updating L2P entries based on the P2L entries after the map management operation corresponding to a completed write operation (corresponding to update to the targeted physical address) i.e. generating entry updated update table corresponding to a target physical memory region; the update table indicate L2P segments updated as data is stored in the target memory region (Fig. 5; Par. 0068-0073; Par. 0042-0044)].
CHO fails to specifically teach the feature: storing of the update target L2P entry in a map update buffer. However, KANG teaches memory controller having improved map update performance, the memory controller: to include a map data manager 210, a map data storage 220, and the map update buffer 230 [Fig. 1; Fig. 2; Par. 0048-0052], the memory controller to control a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data, the map data storage storing physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host [Par. 0056-0058; Par. 0063-0066] wherein: with respect to a command request provided by the map data manager, L2P map data to be updated among the L2P map data stored in the L2P map data storage provided to the memory controller and P2L map data is updated P2L to indicate a mapping relationship between a physical address indicating a location where data according to the request is stored and the received logical address and a physical address of the memory device in which the data is stored [Par. 0048-0051; Par. 0063-0067; Par. 0109-0116].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the instant application to combine the map management operation of CHO with that of KANG, in order to produce a system with improved map update performance.
With respect to claim 7, (US 20220171706 A1) teaches method of operating a data storage device including a storage medium and a memory controller, the method comprising: generating, by the memory controller, mapping information between a physical address of the storage medium and a logical address provided from an external device as a physical-logical address table (P2LT)
[operating method of a memory system featuring data processing operation with respect to a memory device in the memory system comprising memory controller that performs a command operation corresponding to a command received from host system (Fig. 1; Par. 0034-0039)];
reading, by the memory controller, an update target logical- physical address (L2P) segment from a logical-physical address table(L2PT) stored in the storage medium
(map management operation including determining that a map management operation is triggered, based on physical-to-logical (P2L) entries generated after a previous map management operation, the physical-to-logical (P2L) entry corresponding to a physical address of a target memory unit) [Abstract; Fig. 5; Par. 0068-0073; Par. 0036-0037];
storing, by the memory controller, an update target L2P entry from the L2P segment, wherein the update target L2P entry comprises at least one L2P entry to be updated
[when a map management operation is triggered, indicating a map management operation, pre-update table that indicate pre-update statuses of L2P segments including L2P entries to be updated based on the P2L entries because of storing data in the target memory region until the current map management operation is triggered after the previous map management operation is completed (Par. 0046-0047)];
the L2P table includes state entries respectively corresponding to all logical-to-physical (L2P) segments and each of the states indicates whether a corresponding (pre-update) L2P segment includes an L2P entry correspond to a logical address included in the P2L entries) [Abstract; Fig. 5; Par. 0005-0007; Par. 0068-0073; Par. 0042-0044]; and
updating, by the memory controller, the physical address of the update target L2P each time the update target L2P entry is stored
[L2P update to perform an L2P update operation for updating an L2P entry based on a P2L entry to keep the L2P entry up-to-date (Par. 0042-0043; Par. 0005-0007) controller to perform updating L2P entries based on the P2L entries after the map management operation corresponding to a completed write operation (corresponding to update to the targeted physical address) i.e. generating entry updated update table corresponding to a target physical memory region; the update table indicate L2P segments updated as data is stored in the target memory region (Fig. 5; Par. 0068-0073; Par. 0042-0044)].
CHO fails to specifically teach the feature: storing of the update target L2P entry in a map update buffer. However, KANG teaches memory controller having improved map update performance, the memory controller: to include a map data manager 210, a map data storage 220, and the map update buffer 230 [Fig. 1; Fig. 2; Par. 0048-0052], the memory controller to control a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data, the map data storage storing physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host [Par. 0056-0058; Par. 0063-0066] wherein: with respect to a command request provided by the map data manager, L2P map data to be updated among the L2P map data stored in the L2P map data storage provided to the memory controller and P2L map data is updated P2L to indicate a mapping relationship between a physical address indicating a location where data according to the request is stored and the received logical address and a physical address of the memory device in which the data is stored [Par. 0048-0051; Par. 0063-0067; Par. 0109-0116].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the instant application to combine the map management operation of CHO with that of KANG, in order to produce a system with improved map update performance.
With request to claim 13, CHO (US 20220171706) teaches memory controller comprising: a search circuit, when a map update event is triggered, configured to search for at least one update target logical-to-physical address (L2P) entry from a storage medium and store the at least one update target L2P entry in a map update buffer (memory system featuring operating method of a controller including determining that a map management operation is triggered based on physical-to-logical (P2L) entries), searching a pre-update table that indicate pre-update statuses of L2P segments including L2P entries, the L2P table includes state entries respectively corresponding to all logical-to-physical (L2P) segments and each of the states indicates whether a corresponding (pre-update) L2P segment includes an L2P entry correspond to a logical address included in the P2L entries) [Abstract; Fig. 5; Par. 0005-0008; Par. 0038-0044; Par. 0068-0073]; and an update circuit configured to allocate a portion of an internal memory when the map update event is triggered, and update the at least one update target L2P entry on an entry-by-entry basis (L2P update component to perform an L2P update operation for updating an L2P entry based on a P2L entry to keep the L2P entry up-to-date; the map management operation to include a sequence of a pre-update table generation operation for updating an L2P entry based on a P2L entry to keep the L2P entry up-to-date) [Par. 0042-0044; Par. 0047-0049].
CHO fails to specifically teach the feature: update target L2P entry in a map update buffer. However, KANG teaches memory controller having improved map update performance, the memory controller: to include a map data manager 210, a map data storage 220, and the map update buffer 230 [Fig. 1; Fig. 2; Par. 0048-0052], the memory controller to control a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data, the map data storage storing physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host [Par. 0056-0058; Par. 0063-0066] wherein: with respect to a command request provided by the map data manager, L2P map data to be updated among the L2P map data stored in the L2P map data storage provided to the memory controller and indicated a mapping relationship between a physical address indicating a location where data according to the request is stored and the received logical address and a physical address of the memory device in which the data is stored [Par. 0048-0051; Par. 0063-0067; Par. 0109-0116] and .
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the instant application to combine the map management operation of CHO with that of KANG, in order to produce a system with improved map update performance.
With respect to claims 2, CHO and KANG, combined, teach data storage device featuring operating method of a controller, wherein the memory controller comprises: a search circuit configured to store L2P entries to be updated in turn in the map update buffer as the update target L2P entry; and an update circuit, including the map update buffer, configured to update the physical address of the update target L2P entry
(memory device to include a logical to physical (L2P) map data storage, the L2P map data storage to store L2P map data indicating a mapping relationship between a logical address of data provided by the host and a physical address of the memory device 100 in which the data is stored) [KANG’s Par. 0048-0051];
(L2P update component to perform an L2P update operation for updating an L2P entry based on a P2L entry to keep the L2P entry up-to-date, i.e., when the host device updates data, the updated data is stored in a memory unit of a new physical address although the updated data corresponds to the same logical address without any change) [Par. 0042-0044; Par. 0069-0072].
With respect to claims 3, 9, and 14, CHO and KANG, combined, teach data storage device, wherein the update circuit allocates at least a portion of memory in the update circuit to the map update buffer
(the controller allocating map update buffer to store map data addresses indicating locations where the plurality of L2P map segments stored in the L2P map data storage) [KANG’s Par. 0048-0052; Par. 0108-0115];
(L2P memory portion L2PM used to store L2P entries corresponds to pre-update table memory portion PREM used to store a pre-update table) [CHO’s Fig. 4; Par. 0064-0066; Par. 0069-0073].
With respect to claims 4 and 10, CHO and KANG, combined, teach the data storage device, wherein the memory controller is configured to store the L2P segment in the L2PT when all L2P entries to be updated are updated (L2PT maintained in the storage medium, and only some of the L2PT may be referred to in the memory 130. In this case, the controller may load the L2PT in a given segment unit, when attempting to update an L2P entry, the controller to read all L2P segments, including the L2P entry, into the memory) [CHO’s Par. 0060-0061; Par. 0069-0073].
With respect to claims 5 and 11, CHO and KANG, combined, teach the data storage device, wherein the memory controller is configured to store a second L2P entry of the update target L2P segment in the map update buffer while a first L2P entry of the update target L2P segment is updated
(L2P memory portion L2PM used to store L2P entries corresponds to pre-update table memory portion PREM used to store a pre-update table; L2PT maintained in the storage medium with entries to refer to segment addresses in the memory such that the controller, attempting to address segment of the memory refers to updated L2P entries) [CHO’s Fig. 2; Par. 0060-0066; Par. 0069-0073];
(the P2L map data featuring continuous physical addresses mapped to a logical address corresponding to the request) [KANG’s Fig. 8; Par. 0142-0146].
With respect to claims 6 and 12, CHO and KANG, combined, teach the data storage device, wherein the memory controller is configured to: control an overlap between at least a portion of operation for updating a first L2P entry of the update target L2P segment and at least a portion of operation for searching for a second L2P entry of the update target L2P segment and storing the second L2P entry in the map update buffer
(the P2L map data featuring P2L map segment that being a part of all of the plurality of P2L map segments; indicating L2P map data to be updated among the L2P map data stored in the L2P map data storage and physical addresses mapped to a logical address corresponding to request) [KANG’s Fig. 3; Par. 0110-0115];
(L2P memory portion L2PM used to store L2P entries corresponds to pre-update table memory portion PREM used to store a pre-update table; L2PT maintained in the storage medium with entries to refer to segment addresses in the memory such that the controller, attempting to address segment of the memory refers to updated L2P entries) [CHO’s Fig. 2; Par. 0060-0066; Par. 0069-0073].
With respect to claim 8, CHO and KANG, combined, teach method, wherein the storing the update target L2P entry from the L2P segment in a map update buffer and the updating the physical address of the update target L2P entry are performed independently by the memory controller
(memory device to include a logical to physical (L2P) map data storage, the L2P map data storage to store L2P map data indicating a mapping relationship between a logical address of data provided by the host and a physical address of the memory device 100 in which the data is stored) [KANG’s Par. 0048-0051];
(L2P update component to perform an L2P update operation for updating an L2P entry based on a P2L entry to keep the L2P entry up-to-date, i.e., when the host device updates data, the updated data is stored in a memory unit of a new physical address although the updated data corresponds to the same logical address without any change) [CHO’s Par. 0069-0072; Par. 0042-0044].
With respect to claims 15, CHO and KANG, combined, teach the memory controller, wherein the search circuit is configured to search for and read an L2P segment to be updated from the storage medium, and search for the L2P entry to be updated from the L2P segment
(P2L table P2LT_MR0 is referred to through contiguous physical addresses, to which logical address a specific physical address is mapped can be easily checked by referring to the P2L table P2LT_MR0, while a write operation of the storage medium is performed, a P2L entry including a physical address may be first generated, and an L2P entry may be updated based on the P2L entry) [FIG. 5; Par. 0066-0073];
(the P2L map data featuring P2L map segment that being a part of all of the plurality of P2L map segments; indicating L2P map data to be updated among the L2P map data stored in the L2P map data storage and physical addresses mapped to a logical address corresponding to request) [KANG’s Fig. 3; Par. 0110-0115].
With respect to claim 16, CHO and KANG, combined, teach the memory controller, wherein the update circuit is configured to store an updated L2P segment having all of the updated L2P entries in a logical-physical address table (L2PT) stored on the storage medium (L2PT maintained in the storage medium, and only some of the L2PT may be referred to in the memory 130. In this case, the controller may load the L2PT in a given segment unit, when attempting to update an L2P entry, the controller to read all L2P segments, including the L2P entry, into the memory) [CHO’s Par. 0060-0061; Par. 0069-0073].
With respect to claim 17, CHO and KANG, combined, teach the memory controller, wherein the search circuit is configured to store a second L2P entry to be updated in the map update buffer while the update circuit is updating a first L2P entry to be updated
(while the storage medium performing write operation, the pre-update table generator to perform a pre-update table generation operation without waiting for the completion of the write operation of the storage medium; L2P memory portion L2PM used to store L2P entries corresponds to pre-update table memory portion PREM used to store a pre-update table; L2PT maintained in the storage medium with entries to refer to segment addresses in the memory such that the controller, attempting to address segment of the memory refers to updated L2P entries) [CHO’s Fig. 2; Par. 0048-0049; Par. 0060-0066; Par. 0069-0073];
(the P2L map data featuring continuous physical addresses mapped to a logical address corresponding to the request) [KANG’s Fig. 8; Par. 0142-0146].
With respect to claims 18, CHO and KANG, combined, teach the memory controller, further comprising: a storage for storing a physical-to-logical (P2L) table corresponding to the L2P segment
(L2P map data storage to store L2P map data indicating a mapping relationship between a logical address of data provided by the host and a physical address of the memory device in which the data is stored for map data manager generate map control information into the map update buffer) [KANG’s Par. 0107-0115];
(P2L table P2LT_MR0 of the memory region MR0 to include a plurality of P2L entries corresponding to physical addresses PA0 to PAk, each of the P2L entries to indicate mapping information between a corresponding physical address and a logical address of data stored in a memory unit of the corresponding physical address) [CHO’s Par. 0065-0066; Par. 0069-0073].
With respect to claim 19, CHO and KANG, combined, teach the memory controller, wherein the map update event is triggered when the storage is fully stored, when a set number of P2L entries is stored in the storage, or at a set time interval
(map management operation being triggered activates a pre-update table generator generating a pre-update table corresponding to a target memory region based on P2L entries) [CHO’s Par. 0046-0049; Par. 0069-0073];
( L2P map data storage to store L2P map data indicating a mapping relationship between a logical address of data provided by the host and a physical address of the memory device in which the data is stored for map data manager generate map control information into the map update buffer) [KANG’s Par. 0107-0115].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20240184712 A1 (JANG) memory system may include a storage device, an external interface circuit configured to receive a write logical address associated with a write command and a storage location for mapping information and store the write logical address in the storage location; and a processor configured to determine the storage location at which the write logical address is to be stored within a map table and control the storage device to program write data associated with the write command, the map table storing map data between external logical addresses and physical addresses of the storage device.
US 20200065259 A1 (BYUN et al) teaching Memory system and operating method of the memory system including: determining that a map management operation is triggered, based on physical-to-logical (P2L) entries generated after a previous map management operation is completed, wherein the P2L entries respectively correspond to physical addresses of a memory region of a storage medium; generating a pre-update table corresponding to the memory region based on the P2L entries regardless of whether a write operation of the storage medium is completed; updating L2P entries based on the P2L entries after the write operation is completed; and generating, a new original update table by merging the pre-update table and an original update table corresponding to the memory region when the original update table is present in the storage medium and generating, after the L2P entries are updated, the pre-update table as the new original update table when the original update table is not present in the storage medium.
US 10282286 B2 (LI) teaching method including: providing a mapping unit having logical to physical mapping data corresponding to a number of logical addresses, the mapping unit having a variable data unit type associated therewith and comprises a first portion comprising mapping data indicating locations on a memory of a number of physical data units having a size defined by the variable data unit type, and a second portion comprising mapping data indicating locations on the memory of a number of other mapping units of a mapping unit group to which the mapping unit belongs.
US 11301150 B2 (KANG) teaching memory controller having improved map update performance, the memory controller to control a memory device that stores logical to physical map data indicating a mapping relationship between a logical address and a physical address of data, the memory controller to include a map data storage and a map data manager, the map data storage to store physical to logical (P2L) map data generated based on a logical address corresponding to a request received from a host, the map data manager performs a map update operation for the L2P map data by using some of an entire P2L map data stored in the map data storage, according to an amount of the P2L map data stored in the map data storage.
US 12130746 B2 (KURITA et al) teaching controller configured to: generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range; determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous; upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information; and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.
US 11620213 B2 (JIN et al) teaching controller to configure a map table including a map entry associating different address schemes with each other, the controller configured, for performing map table configuration, to find a target map entry among previous map entries in the map table, merge the current map entry into the target map entry to generate a merged map entry when the target map entry is found, and store the merged map entry in the map table, the target map entry and a current map entry including at least some information which is overlapped.
US 9489296 B1 (TOMLIN et al) teaching data storage device to comprise non-volatile memory devices, each configured to store a plurality of physical pages, a controller and a first volatile memory configured to store a logical-to-physical address translation map that enables the controller to determine a physical location of logical pages, the controller to maintain, in the memory devices, a plurality of journals defining physical-to-logical page correspondences, each entry of which associating one or more physical pages to a logical page.
H. Kim, S. Kim, J. Park, G. Byeon and S. Hong, "Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems," in IEEE Access, vol. 13, pp. 18524-18534, 2025.
M. Agarwal and M. Jailia, "Inconsistency in translation lookaside buffer," 2016 International Conference on ICT in Business Industry & Government (ICTBIG), Indore, India, 2016, pp. 1-5.
J. Muck and J. Hays, "Architectural Support For Translation Table Management In Large Address Space Machines," Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, USA, 1993, pp. 39-50.
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/PIERRE MICHEL BATAILLE/ Primary Examiner, Art Unit 2138
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