Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 12 August 2025.
REJECTION NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12159058. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application overlap in scope with the claims of the patent.
Claim 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12417055. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application overlap in scope with the claims of the patent.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 34-36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh (US PG PUB No. 20120170383).
As per claim 34, a non-volatile memory device, comprising:
a memory array comprising an array of memory cells (see Oh FIG 4: 420); and
a peripheral circuit coupled to the memory array and comprising (see Oh FIG 3: 340):
a first buffer coupled to a first pin (see Oh [0036]: “low speed-type buffer”); and
a second buffer coupled to a second pin (see Oh [0036]: “high speed-type buffer”),
wherein while the first buffer is enabled to buffer a command signal or an address signal received from the first pin, the second buffer is enabled to buffer a data signal received from the second pin (see Oh [0056] Table 1)
As per claim 35, the non-volatile memory device according to claim 34,
wherein the peripheral circuit further comprises: an input buffer controller configured to output a first enable signal and a second enable signal (see FIG 3: 340 and [0040]),
wherein the first buffer is enabled by the first enable signal, and the second buffer is enabled by the second enable signal (see [0040]).
As per claim 36, the non-volatile memory device according to claim 34,
wherein the first buffer is only enabled to buffer the command signal or the address signal, and the second buffer is only enabled to buffer the data signal (see Oh [0040]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-27, 29-30, 33, 37-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US PG PUB No. 20120170383) in view of Lee (US PG PUB No. 2022/0011974).
As per claim 21, a non-volatile memory device, comprising:
a first pin configured to receive a command signal or an address signal (see Oh FIG 6: CLE/ALE);
a second pin configured to receive a data signal (see Oh FIG 6: WE);
a first buffer coupled to the first pin (see Oh [0036]: “low speed-type buffers”);
a second buffer coupled to the second pin (see Oh [0036]: “high speed-type buffers”); and
an input buffer controller coupled to the first buffer and the second buffer (see Oh FIG 3: 340 and [0040]), wherein the input buffer controller is configured to:
enable the first buffer, during a first period of time in a command cycle or an address cycle, to buffer the command signal or the address signa (see [0056] Table 1); and
enable the second buffer, during a second period of time in a data input cycle, to buffer the data signal (see [0056] Table 1),
However, Oh does not expressly disclose but in the same field of endeavor Lee discloses
wherein at least part of the second period of time overlaps with the first period of time (Lee [0050]: “For example , while the memory device 100 receives the data DATAa from the memory controller 200 through the first pins of the first channel CH1 , the memory device 100 may receive the command / address CMDa / ADDRa from the memory controller 200 through the second pins of the first channel CH1.”).
It would have been obvious before the effective filing date of the invention to further modify Oh to send command/address in parallel with the data on a first and second pin as taught by Lee.
The suggestion/motivation for doing so would have been for the benefit of improving efficiency (see Lee [0003]).
Therefore it would have been obvious before the effective filing date of the invention to receive command/address in parallel with data as taught by Lee for the benefit improving efficiency to arrive at the invention as specified in the claims.
As per claim 22, the non-volatile memory device according to claim 21,
wherein the input buffer controller is further configured to: disable the second buffer when the data input cycle is ended (see Oh [0017]).
As per claim 23, the non-volatile memory device according to claim 21,
wherein the second buffer is dedicated to buffer the data signal (see Oh [0044]).
As per claim 24, the non-volatile memory device according to claim 21,
wherein the first buffer is only enabled to buffer the command signal or the address signal (see Oh [0056] Table 1) .
As per claim 25, the non-volatile memory device according to claim 21,
wherein the input buffer controller is further configured to: output a first enable signal and a second enable signal (see Oh [0040]).
As per claim 26, the non-volatile memory device according to claim 25,
wherein the first buffer is enabled by the first enable signal, and the second buffer is enabled by the second enable signal (see Oh [0040]).
As per claim 27, the non-volatile memory device of claim 25,
wherein the second buffer comprises: a current-mode logic (CML) circuit coupled to the second pin; and a transistor coupled to the CML circuit and configured to receive the second enable signal (see Oh [0036]).
As per claim 29, the non-volatile memory device according to claim 21,
wherein the first buffer is enabled to buffer the command signal or the address signal with a first speed, and the second buffer is enabled to buffer the data signal with a second speed faster than the first speed (see [0036]).
As per claim 30, the non-volatile memory device according to claim 29,
wherein the first speed is lower than 1 gigahertz(GHz) (see [0036]).
As per claim 33, the non-volatile memory device according to claim 21,
wherein the input buffer controller is further configured to: enable the first buffer to buffer the command signal when a chip enable signal is at a low level (see Oh [0056] Table 1)
As per claim 37, a method for operating a non-volatile memory device, comprising:
enabling a first buffer, during a first period of time in a command cycle or an address cycle, to buffer a command signal or an address signal received from a first pin (see Oh [0040]); and
enabling a second buffer, during a second period of time in a data input cycle, to buffer a data signal received from a second pin (see Oh [0040],
However, Oh does not expressly disclose but in the same field of endeavor Lee discloses
wherein at least part of the second period of time overlaps with the first period of time (Lee [0050]: “For example , while the memory device 100 receives the data DATAa from the memory controller 200 through the first pins of the first channel CH1 , the memory device 100 may receive the command / address CMDa / ADDRa from the memory controller 200 through the second pins of the first channel CH1.”).
It would have been obvious before the effective filing date of the invention to further modify Oh to send command/address in parallel with the data as taught by Lee.
The suggestion/motivation for doing so would have been for the benefit of improving efficiency (see Lee [0003]).
Therefore it would have been obvious before the effective filing date of the invention to receive command/address in parallel with data as taught by Lee for the benefit improving efficiency to arrive at the invention as specified in the claims.
As per claim 38, the method according to claim 37, further comprising:
disabling the second buffer when the data input cycle is ended (see Oh [0056] Table 1).
As per claim 39, the method according to claim 37, further comprising:
outputting an active enable signal, wherein the second buffer is enabled by the active enable signal (see Oh [0040]).
Claim 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US PG PUB No. 20120170383) in view of Lee (US PG PUB No. 2022/0011974) as applied to claim 27 above and further in view of Mitsubori (US PG PUB No. 10902904)
Asp er claim 28, the non-volatile memory device of claim 27,
However, Oh does not expressly disclose but in the same field of endeavor Mitsubori discloses
further comprising a deserializer coupled to the CML circuit (see Mitsubori FIG 2: 225(0) and COL 5 LINES 38-45)
It would have been obvious before the effective filing date of the invention to further implement a deserializer as taught by Mitsubori.
The suggestion/motivation for doing so would have been for the benefit of accuracy and performance (see Mitsubori COL 1 LINE 20-25 and COL 1 LINE 35-40).
Therefore it would have been obvious before the effective filing date of the invention to further implement a deserializer as taught by Mitsubori for the benefit of accuracy and performance to arrive at the invention as specified in the claims.
Claim 31-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US PG PUB No. 20120170383) in view of Lee (US PG PUB No. 2022/0011974) as applied to claim 21 above and further in view of Janzen (US PG PUB No. 2006/0158214)
As per claim 31, the non-volatile memory device according to claim 21,
However, Oh does not expressly disclose but in the same field of endeavor Janzen discloses
wherein the second buffer is enabled when on-die termination (ODT) is enabled.
(see Janzen [0006]).
It would have been obvious before the effective filing date of the invention to further implement a ODT that disables the second buffer as taught by Janzen.
The suggestion/motivation for doing so would have been for the benefit of implementing preferred operating condition (See Janzen [0006]).
Therefore it would have been obvious before the effective filing date of the invention to further enable and disable with ODT as taught by Janzen for the benefit of preferred operating condition to arrive at the invention as specified in the claims.
As per claim 32, the non-volatile memory device according to claim 21,
However, Oh does not expressly disclose but in the same field of endeavor Janzen discloses
wherein the second buffer is disenabled when on-die termination (ODT) is disenabled (see Janzen [0006]).
It would have been obvious before the effective filing date of the invention to further implement a ODT that disables the second buffer as taught by Janzen.
The suggestion/motivation for doing so would have been for the benefit of implementing preferred operating condition (See Janzen [0006]).
Therefore it would have been obvious before the effective filing date of the invention to further enable and disable with ODT as taught by Janzen for the benefit of preferred operating condition to arrive at the invention as specified in the claims.
Claim 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US PG PUB No. 20120170383) in view of Lee (US PG PUB No. 2022/0011974) as applied to claim 37 above and further in view of Hsiao (US PG PUB No. 2017/0115908)
As per claim 40, the method according to claim 37, further comprising:
However, Oh does not expressly disclose but in the same field of endeavor Hsiao discloses
starting an idle mode only when the second buffer is disabled. (see Hsiao FIG 3: S370 and [0019]: “Next, in step S370, the controller determines whether the flash memory enters an idle mode according to the status S2, i.e. it is determined whether the status S2 is"EOh'.”)
[Hsiao discloses entering idle mode only on successful completion of a data programming (i.e., when the second buffer is disabled).]
It would have been obvious before the effective filing date of the invention to further implement an idle mode as taught by Hsiao.
The suggestion/motivation for doing so would have been for the benefit of reliability (see Hsiao [0007]).
Therefore it would have been obvious before the effective filing date of the invention to modify Oh to enter an idle mode as taught by Hsiao for the benefit of reliability to arrive at the invention as specified in the claims.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 20210043240 : A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer (Abstract).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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