Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 12 August 2025.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Such claim limitation(s) is/are:
means for fetching in claim 20 which was taken to correspond to MMU in FIG 1: 100
means for storing in claim 20 which was taken to correspond to Prefetch FIFO Control logic in FIG 1: 205
REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12405900. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the present application are broader than and encompass the subject matter of the claims of the patent.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Campbell (US PG PUB No. 2022/0309001).
As per claim [1,12,20], a method, comprising:
fetching, by a memory management unit (MMU) of a system comprising a system memory and before a request to access data at a client address is received from a client, a first set of one or more first page table entries (see [0030]), wherein the MMU comprises hardware;
storing, in a first translation lookaside buffer, the first set of one or more first page table entries (see [0040]);
storing, in a burst buffer, a plurality of second page table entries (see FIG 3: 308 and [0038]);
fetching, before the request to access data at the client address is received from the client, a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer (see FIG 3: 212a and [0040]); and
storing, in a second translation lookaside buffer, the first set of one or more second page table entries (see FIG 3: 304 and [0040]).
As per claim [2,13], the method of claim 1,
wherein the client address is an address in virtual memory space used by the client (see [0013]).
As per claim [3,14], the method of claim 1,
wherein the client is a video client (see [0022]: “A display 119 (e.g., a screen or a display monitor) is connected to the system bus 102 by the display adapter 115, which can include a graphics controller to improve the performance of graphics intensive applications and a video controller.”)
As per claim 4, the method of claim 3,
wherein the video client is a hardware video client (see [0022]: “A display 119 (e.g., a screen or a display monitor) is connected to the system bus 102 by the display adapter 115, which can include a graphics controller to improve the performance of graphics intensive applications and a video controller.”).
As per claim [5,15], the method of claim 1, wherein:
the client is one of a plurality of system command bus (SCB) clients; and the MMU provides a plurality of MMU instances, each of the plurality of MMU instances corresponding to a respective one of the plurality of SCB clients (see [0022]: “Additional input/output devices are shown as connected to the system bus 102 via a display adapter 115 and an interface adapter 116. In one embodiment, the adapters 106, 107, 115, and 116 can be connected to one or more I/O buses that are connected to the system bus 102 via an intermediate bus bridge (not shown).”).
As per claim 6, the method of claim 1, wherein:
the first set of one or more first page table entries is fetched based at least in part on a virtual address received by the MMU (see [0026]: “ As described herein, the prefetch engine 255 can monitor the demand access stream generated by the processor 210 and issue prefetch requests such that data can be loaded from the larger, slower main memory 208 to the relatively smaller, faster data caches 224, 204 and 203 in order to make it more readily available to the processor 210 when needed.”);
each first page table entry of the first set of one or more first page table entries is associated with a respective page table address (see [0027]: “ In one or more non-limiting embodiments, the page tables 201 can be located in the main memory (e.g., DRAM 208) and the page table walker 202 can be invoked to access the page tables 201, and provide appropriate translation.“);
the plurality of second page table entries is stored in the burst buffer based at least in part on the virtual address (see [0026]); and
the first set of one or more second page table entries is fetched based at least in part on the virtual address (see [0027]).
As per claim 7, the method of claim 1, further comprising:
generating, by the MMU and based at least in part on a virtual address received by the MMU, a virtual address tag associated with the first set of one or more second page table entries; and comparing the virtual address tag with a first portion of the client address (see [0041]).
[A TLB hit is taken to mean a virtual address tag associated with one or more second page table entries are compared with a virtual address received by the MMU.]
As per claim [8,16], the method of claim 7, further comprising:
selecting, in response to a determination that the virtual address tag and the first portion of the client address match and based at least in part on a second portion of the client address different from the first portion, a respective second page table entry of the first set of one or more second page table entries stored at the second translation lookaside buffer (see [0043]).
[A miss causes a lookup and a table walk.]
As per claim [9,17], the method of claim 8, further comprising:
remapping the client address to a physical address of the system memory based at least in part on the respective second page table entry selected by the second translation lookaside buffer (see [0043]).
[A translated address is taken as a remapping the client address to a physical address of the system memory.]
As per claim [10,18], The method of claim 7, further comprising:
fetching, from the burst buffer and in response to a determination that the virtual address tag and the first portion of the client address do not match, a second set of one or more second page table entries different from the first set of one or more second page table entries (see [0043]).
[A TLB miss causes a page table walk.]
As per claim [11,19], the method of claim 10, further comprising:
generating, in response to a determination that none of the first set of one or more first page table entries are associated with the client address and based at least in part on the client address, a second pointer physical address of the system memory; and fetching a second set of one or more first page table entries based at least in part on the second pointer physical address (see [0043]: “When, the VA associated with the missed demand access 300 or the missed L1 prefetch request is not included in the L2 TLB 212 b, the MMU 205 will perform lookups on lower level TLBs or will perform a table walk on the last line of the system-defined real page.”).
[A TLB miss causes a page table walk.]
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 20240273033: Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
