DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 08/12/2025.
Claims 1-20 are pending.
Claims 1-20 are rejected.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the rejections provided herein which must be addressed accordingly.
Priority
Applicant’s priority claim as a continuation of US Application 18/090,449 filed 12/28/2022, now US Patent No. 12,423,002, which claims priority to provisionally filed application 63/295,307 filed 12/30/2021 is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 08/25/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 08/12/2025 are acceptable for examination purposes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,423,002, hereinafter referred to as “Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are of a broader recitation of those in the US Patent as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent may anticipate the claims of the instant application as they are of narrower scope.
Instant Application
US Patent 12,423,002
A memory device comprising: an array of memory cells organized into a plurality of wordlines; and a processing device, operatively coupled to the memory device, to perform processing operations comprising: receiving a program command, the program command specifying a memory unit of the memory device and further specifying data to be programmed to the memory unit, wherein the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines; programming the specified data to the one or more first active data wordlines of the memory unit; and programming a plurality of different data patterns to respective subsets of the group of consecutive retired wordlines.
A memory device comprising: an array of memory cells organized into a plurality of wordlines; and a processing device, operatively coupled to the memory device, to perform processing operations comprising: receiving a program command, the program command specifying a memory unit of the memory device and further specifying data comprising first received data, wherein the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines; and programming the specified data to the memory unit, wherein programming the specified data comprises: programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, programming the first data pattern to the first retired boundary wordline identifying a first retired inner wordline of the group of consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the first retired inner wordline is separated from the one or more first active data wordlines by the first retired boundary wordline, generating a second data pattern comprising a second plurality of threshold voltage levels, wherein the second data pattern is different from the first data pattern, and programming the second data pattern to the first retired inner wordline, wherein programming the specified data to the memory unit does not program at least one of the group of consecutive retired wordlines.
The memory device of claim 1, wherein programming the specified data to the memory unit does not program at least one of the group of consecutive retired wordlines.
The memory device of claim 1, wherein programming the first received data to the one or more first active data wordlines comprises causing the first received data to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the one or more first active data wordlines.
The memory device of claim 1, wherein programming the specified data to the one or more first active data wordlines comprises causing the specified data to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the one or more first active data wordlines.
The memory device of claim 1, wherein programming the first data pattern to the first retired boundary wordline comprises causing the first data pattern to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the first retired boundary wordline that is adjacent to one of the first active data wordlines.
The memory device of claim 1, wherein programming the plurality of different data patterns to the respective subsets of the group of consecutive retired wordlines comprises: identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines; generating a first data pattern comprising a first plurality of threshold voltage levels; programming the first data pattern to the first retired boundary wordline; identifying a first retired inner wordline of the group of consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the first retired inner wordline is separated from the one or more first data active wordlines by the first retired boundary wordline; generating a second data pattern comprising a second plurality of threshold voltage levels; and programming the second data pattern to the first retired inner wordline.
The memory device of claim 3, wherein the memory device further comprises a plurality of bitlines, each of the plurality of wordlines intersects one of the plurality of bitlines, and each of the first plurality of threshold voltage levels corresponds to a respective one of the plurality of bitlines.
The memory device of claim 4, wherein programming the first data pattern to the first retired boundary wordline comprises causing the first data pattern to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the first retired boundary wordline that is adjacent to one of the first active data wordlines.
The memory device of claim 4, wherein each of the first plurality of threshold voltage levels is programmed to a respective one of the plurality of memory cells that is located at an intersection between the first retired boundary wordline and the respective one of the plurality of bitlines.
The memory device of claim 4, wherein the memory device further comprises a plurality of bitlines, each of the plurality of wordlines intersects one of the plurality of bitlines, and each of the first plurality of threshold voltage levels corresponds to a respective one of the plurality of bitlines.
The memory device of claim 1, wherein each of the first plurality of threshold voltage levels is determined based on a respective pseudo-random value.
The memory device of claim 6, wherein each of the first plurality of threshold voltage levels is programmed to a respective one of the plurality of memory cells that is located at an intersection between the first retired boundary wordline and the respective one of the plurality of bitlines.
The memory device of claim 1, wherein each of the first plurality of threshold voltage levels is a median threshold voltage level between a lowest threshold voltage level and a highest threshold voltage level of the memory device.
A method comprising: receiving a program command, the program command specifying a memory unit of a memory device comprising an array of memory cells organized into a plurality of wordlines, the program command further specifying data to be programmed to the memory unit, wherein the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines; programming the specified data to the one or more first active data wordlines of the memory unit; and programming a plurality of different data patterns to respective subsets of the group of consecutive retired wordlines.
The memory device of claim 1, wherein each of the second plurality of threshold voltage levels is a highest threshold voltage level of the memory device, and each of the first plurality of threshold voltage levels is determined based on a respective pseudo-random value.
The method of claim 8, wherein programming the specified data to the memory unit does not program at least one of the group of consecutive retired wordlines.
The memory device of claim 1, wherein the plurality of wordlines further includes one or more second active data wordlines, and wherein the one or more second active data wordlines are separated from the one or more first active data wordlines by the group of consecutive retired wordlines, wherein the group of consecutive retired wordlines further includes a second retired boundary wordline that is adjacent to one of the second active data wordlines, and wherein programming the specified data to the memory unit further comprises: programming the first data pattern to the second retired boundary wordline.
The method of claim 8, wherein programming the specified data to the one or more first active data wordlines comprises causing the specified data to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the one or more first active data wordlines.
The memory device of claim 9, wherein the specified data further comprises second received data, and wherein programming the specified data to the memory unit further comprises programming the second received data to the one or more second active data wordlines.
The method of claim 8, wherein programming the plurality of different data patterns to the respective subsets of the group of consecutive retired wordlines comprises: identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines; generating a first data pattern comprising a first plurality of threshold voltage levels; programming the first data pattern to the first retired boundary wordline; identifying a first retired inner wordline of the group of consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the first retired inner wordline is separated from the one or more first data active wordlines by the first retired boundary wordline; generating a second data pattern comprising a second plurality of threshold voltage levels; and programming the second data pattern to the first retired inner wordline.
The memory device of claim 9, wherein programming the specified data to the memory unit further comprises: identifying a first retired inner wordline and a second retired inner wordline of the group of consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the second retired inner wordline is adjacent to the second retired boundary wordline; generating a second data pattern comprising a second plurality of threshold voltage levels; and programming the second data pattern to the first retired inner wordline and to the second retired inner wordline.
The method of claim 11, wherein programming the first data pattern to the first retired boundary wordline comprises causing the first data pattern to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the first retired boundary wordline that is adjacent to one of the first active data wordlines.
The memory device of claim 11, wherein each of the second plurality of threshold voltage levels is a highest threshold voltage level of the memory device, and each of the first plurality of threshold voltage levels is determined based on a respective pseudo-random value.
The method of claim 11, wherein the memory device further comprises a plurality of bitlines, each of the plurality of wordlines intersects one of the plurality of bitlines, and each of the first plurality of threshold voltage levels corresponds to a respective one of the plurality of bitlines.
The memory device of claim 1, wherein the program command further specifies a physical address that identifies the memory unit.
The method of claim 13, wherein each of the first plurality of threshold voltage levels is programmed to a respective one of the plurality of memory cells that is located at an intersection between the first retired boundary wordline and the respective one of the plurality of bitlines.
A method comprising: receiving a program command, the program command specifying a memory unit of a memory device and further specifying data comprising first received data and second received data, wherein the memory device includes a plurality of wordlines that includes one or more first active data wordlines and a group of consecutive retired wordlines, wherein the group of consecutive retired wordlines includes a first retired boundary wordline that is adjacent to one of the first active data wordlines, and further includes one or more second retired wordlines; generating a first data pattern comprising a first plurality of threshold voltage levels; programming the first data pattern to a first plurality of memory cells of the memory unit, wherein the first plurality of memory cells corresponds to the first retired boundary wordline, wherein programming the first data pattern to the first plurality of memory cells reduces a voltage difference between at least one cell of the one of the first active data wordlines and at least one cell of at least one of the one or more second retired wordlines, wherein programming the first data pattern does not program at least one of the group of consecutive retired wordlines; generating a second data pattern comprising a second plurality of threshold voltage levels, wherein the second data pattern is different from the first data pattern; programming the second data pattern to a second plurality of memory cells of the memory unit, wherein the second plurality of memory cells corresponds to a first retired inner wordline of the group consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the first retired inner wordline is separated from the one or more first active data wordlines by the first retired boundary wordline; and causing the first received data to be programmed to a second plurality of memory cells of the memory unit, wherein the second plurality of memory cells corresponds to the one or more first active data wordlines.
A non-transitory computer-readable storage medium storing instructions which, when executed by a processing device, cause the processing device to perform operations comprising: receiving a program command, the program command specifying a memory unit of a memory device comprising an array of memory cells organized into a plurality of wordlines, the program command further specifying data to be programmed to the memory unit, wherein the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines; programming the specified data to the one or more first active data wordlines of the memory unit; and programming a plurality of different data patterns to respective subsets of the group of consecutive retired wordlines.
The method of claim 14, wherein programming the first data pattern to the first plurality of memory cells reduces an amount of charge loss between the at least one cell of the one of the first active data wordlines and the at least one cell of at least one of the one or more second retired wordlines.
The non-transitory computer-readable storage medium of claim 15, wherein programming the specified data to the memory unit does not program at least one of the group of consecutive retired wordlines.
The method of claim 14, wherein programming the first data pattern to the first plurality of memory cells offsets a voltage reduction in the at least one cell of the one of the first active data wordlines caused by a negative pillar potential region associated with the at least one cell of at least one of the one or more second retired wordlines.
The non-transitory computer-readable storage medium of claim 15, wherein programming the specified data to the one or more first active data wordlines comprises causing the specified data to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the one or more first active data wordlines.
A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform processing operations comprising: receiving a program command, the program command specifying a memory unit of a memory device and further specifying data comprising first received data, wherein the memory device comprises an array of memory cells organized into a plurality of wordlines, wherein the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines; and programming the specified data to the memory unit, wherein programming the specified data comprises: programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, programming the first data pattern to the first retired boundary wordline, identifying a first retired inner wordline of the group of consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the first retired inner wordline is separated from the one or more first active data wordlines by the first retired boundary wordline, generating a second data pattern comprising a second plurality of threshold voltage levels, wherein the second data pattern is different from the first data pattern, and programming the second data pattern to the first retired inner wordline, wherein programming the specified data to the memory unit does not program at least one of the group of consecutive retired wordlines.
The non-transitory computer-readable storage medium of claim 15, wherein programming the plurality of different data patterns to the respective subsets of the group of consecutive retired wordlines comprises: identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines; generating a first data pattern comprising a first plurality of threshold voltage levels; programming the first data pattern to the first retired boundary wordline; identifying a first retired inner wordline of the group of consecutive retired wordlines, wherein the first retired inner wordline is adjacent to the first retired boundary wordline, and the first retired inner wordline is separated from the one or more first data active wordlines by the first retired boundary wordline; generating a second data pattern comprising a second plurality of threshold voltage levels; and programming the second data pattern to the first retired inner wordline.
The non-transitory computer-readable storage medium of claim 18, wherein programming the first data pattern to the first retired boundary wordline comprises causing the first data pattern to be programmed to a plurality of memory cells of the memory unit, wherein the plurality of memory cells corresponds to the first retired boundary wordline that is adjacent to one of the first active data wordlines.
The non-transitory computer-readable storage medium of claim 18, wherein the memory device further comprises a plurality of bitlines, each of the plurality of wordlines intersects one of the plurality of bitlines, and each of the first plurality of threshold voltage levels corresponds to a respective one of the plurality of bitlines, and wherein each of the first plurality of threshold voltage levels is programmed to a respective one of the plurality of memory cells that is located at an intersection between the first retired boundary wordline and the respective one of the plurality of bitlines.
Regarding claim 1, the claim of the instant application is substantially similar to that of Claim 1 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application.
Regarding claim 2 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 3 of the instant application, the limitations are substantially identical to limitations of claim 2 of the Patent.
Regarding claim 4 of the instant application, the limitations are substantially identical to limitations of claim 1 of the Patent.
Regarding claim 5 of the instant application, the limitations are substantially identical to claim 1 and claim 3 of the Patent.
Regarding claim 6 of the instant application, the limitations are substantially identical to limitations of claim 4 of the Patent.
Regarding claim 7 of the instant application, the limitations are substantially identical to claim 5 of the Patent.
Regarding claim 8 of the instant application, the limitations are substantially identical to claim 14 of the Patent on a similar basis as identified for claim 1 of the instant application.
Regarding claim 9 of the instant application, the limitations are substantially identical to claim 14 of the Patent.
Regarding claim 10 of the instant application, the limitations are substantially identical to limitations of claim 14 of the Patent.
Regarding claim 11 of the instant application, the limitations are substantially identical to limitations of claim 14 of the Patent
Regarding claim 12 of the instant application, the limitations are substantially identical to claim 14 of the Patent.
Regarding claim 13 of the instant application, the limitations are substantially identical to limitations of claim 14 and claim 4 of the Patent. It would be obvious to one of ordinary skill in the art that the claimed structure of the bitlines as recited in the US Patent Claim 4 may be incorporated in the method steps of controlling the memory device comprising said bitlines as recited in Claim 14.
Regarding claim 14 of the instant application, the limitations are substantially identical to claim 14 and claim 5 of the Patent for similar reasons as provided above for claim 13.
Regarding claim 15 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 16 of the instant application, the limitations are substantially identical to limitations of claim 17 of the Patent.
Regarding claim 17 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 18 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 19 of the instant application, the limitations are substantially identical to claim 17 of the Patent.
Regarding claim 20 of the instant application, the limitations are substantially identical to claim 17 and claim 4 and claim 5 of the Patent for similar reasons as provided above for claim 13 and claim 14 of the instant application.
This is a nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wood et al. (US 2012/0063231) – Paragraphs [0241-242] wherein a wordline restriction module controlling access to wordlines is discussed.
Liou (US 9,805,782) – Column 6n lines 34-57 wherein boundary wordline refresh operations is discussed.
Kim et al. (US 2017/0075593) – Paragraphs [0018-20] wherein boundary wordline disturb is discussed.
Jeloka et al. (US 2020/0066358) – Paragraphs [0021-37] wherein active and inactive wordline management is discussed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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