DETAILED ACTION
Claims 1-20 are pending.
Priority: 8/27/2024; 10/16/2024(FP)
Assignee: Samsung
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 2-18 is/are objected to as being dependent upon a rejected base claim, but would be allowable based on the prior art, if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim(s) 20 is/are allowed over the prior art.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1–11, 13–16, and 19–20 are rejected under 35 U.S.C. § 101 because the claimed inventions are directed to a judicial exception (an abstract idea) without reciting additional elements that integrate the exception into a practical application or amount to significantly more.
A. Step 2A, Prong One — Claim 1 Recites an Abstract Idea
Claim 1 recites, in substance: (i) mapping upper-bit data to a shorter flag representation; (ii) counting occurrences of the resulting flags; and (iii) deriving index information from the count. These limitations describe mathematical relationships and calculations: a relationship between an input binary pattern and a replacement binary representation, an arithmetic tally of occurrences, and derivation of a count-based index. They therefore fall within the “mathematical concepts” grouping of abstract ideas.
The same limitations also concern encoding, manipulating, and reorganizing information. Federal Circuit precedent treats encoding or decoding data, converting information from one format to another, and gathering or combining data as abstract where the claims focus on the information transformation rather than a claimed improvement in computer or memory operation.
Step 2A, Prong Two — Claim 1 Does Not Integrate the Exception
The elements beyond the identified mathematical/data-encoding operations are the memory device, memory cells, and memory controller, together with functional component labels for carrying out the operations. These elements place the abstract operations in a data-storage environment, but claim 1 does not require the generated index to be written to the memory cells, used to control a physical memory operation, or used to detect or correct an error. Nor does claim 1 require a particular physical arrangement of memory cells, buses, controller circuitry, or timing logic.
Although the specification discusses reducing data size and protecting reliability, the technological benefit relevant to eligibility must be reflected in the claim. Claim 1 ends with generation of count-based information. It does not claim the disclosed comparison of expected and actual counts or a resulting response to corrupted compressed data. The claim therefore improves the content or format of the data rather than the functioning of the memory device or controller itself.
Limiting the information-processing scheme to “input data” in a “weight bundle” associated with a memory device is a field-of-use limitation and technological environment. It does not impose a meaningful limit on the abstract operations. The claim as a whole thus does not integrate the abstract idea into a practical application.
C. Step 2B — Claim 1 Does Not Recite Significantly More
The additional memory hardware is recited at a high level of generality and performs its ordinary functions. The specification describes the memory device broadly as any of numerous conventional volatile or nonvolatile memory types and describes the memory controller as including a processor that controls the memory device and transmits or receives data. See Specification [0025]–[0029], [0040]–[0041]. These statements support the finding that the claimed memory device, memory cells, and controller—apart from the abstract encoding/counting scheme—are well-understood, routine, and conventional components used in their ordinary manner.
The flag encoder, local counter, and index generator do not supply an inventive concept because the functions attributed to them constitute the identified exception itself. Even assuming the particular encoding/counting concept were novel, novelty of the abstract idea does not convert it into patent-eligible subject matter. Considered as an ordered combination, the claim merely directs generic memory-controller logic to perform the abstract sequence of encode, count, and generate metadata. It therefore does not amount to significantly more.
D. Dependent Claims 2–5
Claims 2–5 do not cure the deficiency. Claim 2 adds combining a flag with lower bits to form compressed data. Claim 3 adds a second flag and determines whether upper bits fall within or outside a predetermined range. Claims 4 and 5 add separate tallies for the two flag types and place both tallies in the index. These limitations add further binary mapping, comparison, arithmetic counting, and organization of information—additional instances of the same mathematical/data-manipulation exception. They do not require a physical memory operation or use the resulting metadata to detect or correct an error.
E. Dependent Claims 6–11
Claims 6–10 add inverse data-format operations: decoding a flag into upper bits, recombining upper and lower bits, omitting a flag, and producing data of a larger or smaller size. Encoding and decoding information and converting between data formats remain abstract information processing. The recited decompressor and flag decoder are functional labels for performing those operations and do not require specialized circuitry.
Claim 11 adds counting first and second flags in output data to produce actual count values. That limitation is an arithmetic tally and does not itself compare the actual values with expected values or determine that an error occurred. Thus, claims 6–11 remain directed to the identified abstract idea without a practical application or inventive concept.
F. Dependent Claims 13–16
Claims 13–16 aggregate count information over a “global block,” generate a header from global counts, count flags in an output global block, and retrieve expected global count values from the header. These limitations add hierarchical aggregation, metadata generation, and metadata retrieval. They continue to manipulate and organize numerical information.
Notably, claim 16 stops at obtaining expected global count values. The actual comparison and error determination are not recited until claim 17. Accordingly, claims 13–16 do not themselves claim the technological use that could distinguish mere check-data generation from a specific error-detection application.
G. Rejection of Claim 19
A. Step 2A
Claim 19 recites a memory controller comprising a flag encoder that maps upper bits to a first flag, a local counter that tallies first flags, and an index generator that generates an index based on the tally. For the reasons stated for claim 1, these limitations recite mathematical relationships and calculations and the abstract encoding and reorganization of data.
Claim 19 is broader than claim 1 in a material respect: it does not require that the index contain the count, that a weight bundle be written to or read from the memory device, or that the index be used for error detection. The phrase “controlling a memory device” merely states the intended environment for the controller. The claim does not recite a control operation that changes the functioning of the memory device.
B. Step 2B
The controller and its functional subcomponents merely implement the abstract sequence using generic processing logic. The claim does not recite a nonconventional hardware arrangement or a specific physical memory-control mechanism. Individually and as an ordered combination, the additional elements therefore do not supply significantly more than the abstract idea.
H. Rejection of Claim 20
A. Step 2A, Prong One
Claim 20 recites: compressing upper bits into a first flag; attaching a second flag to other input data; counting first and second flags; and generating index information from the resulting count values. These steps expressly recite binary mapping, arithmetic counting, and derivation of metadata from the counts. They therefore recite mathematical concepts and abstract data encoding and organization.
B. Step 2A, Prong Two
The preamble states that the method operates a data storage device, but the body does not require storing the resulting weight bundle, writing the index to memory cells, reading the bundle, detecting an error, correcting an error, retransmitting data, or controlling a physical memory operation. The claimed method begins with data and ends with differently represented data plus descriptive index information. The data storage environment therefore does not integrate the exception into a practical application.
C. Step 2B
Claim 20 recites no additional physical component or unconventional ordered combination beyond the abstract steps themselves. The generic reference to a data storage device is an instruction to apply the data-processing scheme in a particular technological environment. It does not add an inventive concept. Claim 20 therefore does not amount to significantly more than the identified abstract idea.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al.(20240289014).
As per claim 1, Lee discloses:
A data storage device(Lee, [0020 -- The storage device 50 may include a memory device 100 and a memory controller 200 for controlling an operation of the memory device]) comprising:
a memory device comprising memory cells(Lee, [0066 -- Referring to FIG. 6, the memory device 100 may include a memory cell array ]);
and a memory controller configured to control the memory device(Lee, [0029 -- The data compressor 182 may generate a plurality of compressed-data “chunks,” each chunk comprised of “target bits” and position-information bits, which specify the position or location of the target bits in the original data read from the memory cells], [0075 -- The encoding device 170 may include a data manager 181 and the data compressor 182. The encoding device 170 may divide read data into sub-data groups, and generate a maximum of one compressed-data chunk per sub-data group]), wherein the memory controller comprises:
a compressor configured to perform a compression operation on at least one piece of input data, among a plurality of pieces of input data included in a weight bundle(Lee, [0057 -- In the compression circuit embodiment identified by reference numeral 410, original data may be divided into N partial data. In the compression circuit embodiment identified by reference numeral 420, original data may be divided into N sub-data groups. In the “410” embodiment, M compression circuits are included per one partial data]), the compressor comprises:
a flag encoder configured to compress upper bits of each piece in the at least one piece of input data, among the plurality of pieces of the input data included in the weight bundle, into a first flag(Lee, [0057 -- The number of compression circuits 415 may therefore be N*M. In the “420” embodiment, one compression circuit is included per one sub-data group. Therefore, the 420 embodiment the number of required compression circuits]);
a first local counter configured to count a number of first flags and generates a first count value(Lee, [0028 -- The data compressor 182 may determine a number of “target bits” in a sub-data group, which have a first-value bit, i.e., a bit having the first value logic 1]);
and an index generator configured to generate an index for the weight bundle based on the first count value(Lee, [0029 -- The data compressor 182 may generate a plurality of compressed-data “chunks,” each chunk comprised of “target bits” and position-information bits, which specify the position or location of the target bits in the original data read from the memory cells]), wherein the index comprises information on a number of pieces of input data compressed using the first flag(Lee, [0052 -- The data compressor 182 may generate a plurality of compressed-data chunks including a logic value of target bits and position information representing a position of the target bits in the original data]), among the plurality of pieces of the input data included in the weight bundle(Lee, [0063 -- the data compressor 182 may generate a plurality of compressed-data chunks, which comprise a logic value of the target bits and position information representing or identifying a position of the target bits in the original data]).
As per claim 19, Lee discloses:
A memory controller controlling a memory device(Lee, [0029 -- The data compressor 182 may generate a plurality of compressed-data “chunks,” each chunk comprised of “target bits” and position-information bits, which specify the position or location of the target bits in the original data read from the memory cells], [0075 -- The encoding device 170 may include a data manager 181 and the data compressor 182. The encoding device 170 may divide read data into sub-data groups, and generate a maximum of one compressed-data chunk per sub-data group]), the memory controller comprising:
a flag encoder configured to compress upper bits of each piece in at least one piece of input data, among a plurality of pieces of input data included in a weight bundle, into a first flag(Lee, [0057 -- The number of compression circuits 415 may therefore be N*M. In the “420” embodiment, one compression circuit is included per one sub-data group. Therefore, the 420 embodiment the number of required compression circuits]);
a first local counter configured to count a number of first flags and generates a first count value(Lee, [0028 -- The data compressor 182 may determine a number of “target bits” in a sub-data group, which have a first-value bit, i.e., a bit having the first value logic 1]);
and an index generator configured to generate an index for the weight bundle based on the first count value(Lee, [0029 -- The data compressor 182 may generate a plurality of compressed-data “chunks,” each chunk comprised of “target bits” and position-information bits, which specify the position or location of the target bits in the original data read from the memory cells]).
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jung et al.(9172396), involves determining the actual data size of special data stored in a preset size unit storage space. The determined actual data size of the spacial data is taken for setting the size of compressed storage space for compressing and storing the spacial data. The flag data is generated with the actual data size of the spacial data. The generated flag data is stored in set area of compressed storage space having preset size. The actual data of spacial data is stored in remaining area of compressed storage space(Jung, abstract).
Shen et al.(20260074713), involves identifying a number of leading bits to remove from each data sample in a block of the data samples for the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits (LSBs) from each data sample in the block of the data samples. A bitstream comprising the block of compressed data samples and an indication of a type of compression applied to a block of the data samples are generated. The generated bitstream is output(Yamigawa, abstract).
Yamigawa et al.(20210258020) involves device that has a predetermined number of entry area that stores first data correspondence with the second data in which a size is smaller than first data. The entry area of the predetermined number is divided into several bank areas. Each number is smaller than the predetermined number or the predetermined number searches for the entry area that forms the corresponding bank area determined by the determination portion. The stored data of second data is outputted, when second data corresponding to first data are stored. The second data corresponding to first data are acquired, when the second data corresponding to first data are not stored. A processing portion that registers the acquired second data in an entry area in which the other second data is not stored and outputs the first data(Yamigawa, abstract).
Yap et al.(20170285960), involves a memory controller that has a connection to a memory. A tag for each section is encoded to indicate the one of the zero value, the full match, the partial match, and the no match. A literal is encoded when the section is the no match. An index to the entry is in the dictionary when the section is the full match. An index to the entry is in the dictionary and non-matching bits when the section is the partial match. An entry in the dictionary with a value of a section is updated when the section is the no match(Yap, abstract).
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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