DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 08/13/2025. Claims 1-22 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 07/27/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The IDS filed on 08/13/2025 is empty. That is, no reference is listed in this IDS. The IDS has been entered into the record.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
As enumerated in the table below, independent claims 1, 10, 14, and 17 of the instant application are anticipated by independent claims 1, 10, and 12 of US Patent 12,411,609.
Analysis
Instant Application
US Patent 12,411,609
Anticipation
1. A memory device, comprising:
an array of memory cells, including a plurality of memory cells;
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first result corresponding to a first set of memory cells at a first voltage, wherein the first result includes a first number of bits related to two read results at the first voltage and a first offset voltage, and the first offset voltage offsets with respect to the first voltage;
obtain a second result corresponding to the first set of memory cells at a second voltage adjusted based on the first voltage and the first result, wherein the second result includes a second number of bits related to two read results at the second voltage and a second offset voltage, and the second offset voltage offsets with respect to the second voltage; and
]determine a read voltage in accordance with the first result and the second result.
1. A memory device, comprising:
an array of memory cells, including a plurality of memory cells,
wherein a preset number of the plurality of memory cells form a code word;
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes a number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words.
Obvious in view of Tokutomi et al. US 2019/0130968
2. The memory device of claim 1, wherein: the first number of bits comprises a first count of bits that are flipped in the two read results at the first voltage and the first offset voltage; and the second number of bits comprises a second count of bits that are flipped in the two read results at the second voltage and the second offset voltage.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
3. The memory device of claim 1, wherein the peripheral circuit is configured to: perform, with the first voltage, the first offset voltage, the second voltage, and the second offset voltage, read operations on the first set of memory cells to obtain corresponding read results under a single level read mode.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
4. The memory device of claim 1, wherein the peripheral circuit is configured to: in response to the first result being less than or equal to a first preset value and the second result being less than or equal to a second preset value, determine a voltage corresponding to a minimum value between the first result and the second result to be the read voltage, wherein the second preset value is lower than the first preset value.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
5. The memory device of claim 4, wherein the peripheral circuit is further configured to: in response to the first result being less than or equal to the first preset value, adjust the first voltage with a preset step size to obtain the second voltage; wherein: the preset step size is greater than a preset voltage, a first difference between the first voltage and the first offset voltage is less than the preset voltage; and a second difference between the second voltage and the second offset voltage is less than the preset voltage.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
6. The memory device of claim 5, wherein the peripheral circuit is further configured to: in response to the second result being less than the first preset value and greater than the second preset value, adjust the second voltage with the preset step size.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
7. The memory device of claim 4, wherein the peripheral circuit is further configured to: in response to the first result being greater than the first preset value, perform multiple adjustments to the first voltage, and obtain a plurality of first results respectively corresponding to the first set of memory cells at a plurality of adjusted first voltages; and in response to the plurality of first results being all greater than the first preset value, adjust the first set of memory cells to obtain a second set of memory cells, wherein a number of memory cells corresponding to the second set of memory cells is less than a number of memory cells corresponding to the first set of memory cells.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
8. The memory device of claim 1, wherein the peripheral circuit is further configured to: perform a logical operation on a first read result corresponding to a read operation with the first voltage and a second read result corresponding to a read operation with the first offset voltage, to obtain a first operation result, wherein the first result is obtained based on the first operation result; and perform the logical operation on a third read result corresponding to a read operation with the second voltage and a fourth read result corresponding to a read operation with the second offset voltage, to obtain a second operation result, wherein the second result is obtained based on the second operation result; and wherein the peripheral circuit comprises: a first latch configured to store the first read result and the third read result; a second latch configured to store the second read result and the fourth read result; and a third latch configured to store the first operation result and the second operation result.
Claim 1
Obvious in view of Tokutomi et al. US 2019/0130968
9. The memory device of claim 1, wherein: each memory cell of the first set of memory cells is configured to store M bits of data, a read operation with N levels of read voltage is performed on the first set of memory cells to read M type pages of data, each type page corresponds to at least one level of read voltage, the M and the N are both integers greater than 1, and N=2.sup.M−1; and the peripheral circuit is configured to: determine the read voltage corresponding to each level of read voltage at one type of page.
Claim 1
Anticipation
10. A memory system, comprising: a memory controller; and a memory device, comprising: an array of memory cells, including a plurality of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a first set of memory cells at a first voltage, wherein the first result includes a first number of bits related to two read results at the first voltage and a first offset voltage, wherein the first offset voltage offsets with respect to the first voltage; obtain a second result corresponding to the first set of memory cells at a second voltage adjusted based on the first voltage and the first result, wherein the second result includes a second number of bits related to two read results at the second voltage and a second offset voltage, wherein the second offset voltage offsets with respect to the second voltage; and send a read voltage to the memory controller, wherein the read voltage is determined in accordance with the first result and the second result.
10. A memory system, comprising: one or more memory device, comprising: an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality memory cells form a code word; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes the number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words; and a memory controller coupled to the memory device and controlling the memory device.
Obvious in view of Tokutomi et al. US 2019/0130968
11. The memory system of claim 10, wherein: the first number of bits comprises a first count of bits that are flipped in the two read results at the first voltage and the first offset voltage; and the second number of bits comprises a second count of bits that are flipped in the two read results at the second voltage and the second offset voltage.
Claim 10
Obvious in view of Tokutomi et al. US 2019/0130968
12. The memory system of claim 10, wherein the memory device is configured to: perform, with the first voltage, the first offset voltage, the second voltage, and the second offset voltage, read operations on the first set of memory cells to obtain corresponding read results under a single level read mode.
Claim 10
Obvious in view of Tokutomi et al. US 2019/0130968
13. The memory system of claim 10, wherein the memory device is configured to: in response to the first result being less than or equal to a first preset value and the second result being less than or equal to a second preset value, determine a voltage corresponding to a minimum value between the first result and the second result to be the read voltage, wherein the second preset value is lower than the first preset value.
Claim 10
Anticipation
14. A method of operating a memory device, comprising: obtaining a first result corresponding to a first set of memory cells at a first voltage, wherein the first result includes a first number of bits related to two read results at the first voltage and a first offset voltage, and the first offset voltage offsets with respect to the first voltage; obtaining a second result corresponding to the first set of memory cells at a second voltage adjusted based on the first voltage and the first result, wherein the second result includes a second number of bits related to two read results at the second voltage and a second offset voltage, and the second offset voltage offsets with respect to the second voltage; and determining a read voltage in accordance with the first result and the second result.
12. A method for operating a memory device, comprising: obtaining a first result corresponding to at least one of code words at a target read voltage, wherein the first result includes a number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, wherein a difference between the first read voltage and the second read voltage is less than a preset voltage, and wherein the memory device includes an array of memory cells, the array of memory cells includes a plurality of memory cells, and a preset number of the plurality memory cells form a code word; adjusting the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtaining a first result corresponding to at least one of the code words at the adjusted read voltage; and determining a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words.
Obvious in view of Tokutomi et al. US 2019/0130968
15. The method of claim 14, further comprising: in response to the first result being less than or equal to a first preset value and the second result being less than or equal to a second preset value lower than the first preset value, determining a voltage corresponding to a minimum value between the first result and the second result to be the read voltage.
Claim 12
Obvious in view of Tokutomi et al. US 2019/0130968
16. The method of claim 15, further comprising: in response to the first result being less than or equal to the first preset value, adjusting the first voltage with a preset step size to obtain the second voltage; wherein the preset step size is greater than a preset voltage, a first different between the first voltage and the first offset voltage is less than the preset voltage, and a second different between the second voltage and the second offset voltage is less than the preset voltage; in response to the first result being greater than the first preset value, performing multiple adjustments to the first voltage, and obtaining a plurality of first results respectively corresponding to the first set of memory cells at a plurality of adjusted first voltages; in response to the plurality of first results being all greater than the first preset value, adjusting the first set of memory cells to obtain a second set of memory cells, wherein a number of memory cells corresponding to the second set of memory cells is less than a number of memory cells corresponding to the first set of memory cells; and in response to the second result being less than the first preset value and greater than the second preset value, adjusting the second voltage with the preset step size.
Claim 12
Anticipation
17. A memory system, comprising: a memory device comprising an array of memory cells, including a plurality of memory cells; and a memory controller coupled to the memory device and configured to: obtain a first result corresponding to a first set of memory cells at a first voltage, wherein the first result includes a first number of bits related to two read results at the first voltage and a first offset voltage, and the first offset voltage offsets with respect to the first voltage; obtain a second result corresponding to the first set of memory cells at a second voltage adjusted based on the first voltage and the first result, wherein the second result includes a second number of bits related to two read results at the second voltage and a second offset voltage, and the second offset voltage offsets with respect to the second voltage; and determine a read voltage in accordance with the first result and the second result.
10. A memory system, comprising: one or more memory device, comprising: an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality memory cells form a code word; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes the number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words; and a memory controller coupled to the memory device and controlling the memory device.
Obvious in view of Tokutomi et al. US 2019/0130968
18. The memory system of claim 17, wherein: the first number of bits comprises a first count of bits that are flipped in the two read results at the first voltage and the first offset voltage; and the second number of bits comprises a second count of bits that are flipped in the two read results at the second voltage and the second offset voltage.
Claim 10
Obvious in view of Tokutomi et al. US 2019/0130968
19. The memory system of claim 17, wherein the memory controller is configured to: in response to the first result being less than or equal to a first preset value and the second result being less than or equal to a second preset value, determine a voltage corresponding to a minimum value between the first result and the second result to be the read voltage, wherein the second preset value is lower than the first preset value.
Claim 10
Obvious in view of Tokutomi et al. US 2019/0130968
20. The memory system of claim 19, wherein the memory controller is configured to: send a first instruction to the memory device to obtain the first result; receive the first result from the memory device; and in response to the first result being less than or equal to the first preset value, adjust the first voltage with a preset step size to obtain the second voltage; wherein: the preset step size is greater than a preset voltage, a first difference between the first voltage and the first offset voltage is less than the preset voltage; and a second difference between the second voltage and the second offset voltage is less than the preset voltage.
Claim 10
Obvious in view of Tokutomi et al. US 2019/0130968
21. The memory system of claim 20, wherein the memory controller is configured to: send a second instruction to the memory device to obtain the second result; receive the second result from the memory device; and in response to the second result being less than the first preset value and greater than the second preset value, adjust the second voltage with the preset step size.
Claim 10
Obvious in view of Tokutomi et al. US 2019/0130968
22. The memory system of claim 19, wherein the memory controller is configured to: in response to the first result being greater than the first preset value, perform multiple adjustments to the first voltage, and obtain a plurality of first results respectively corresponding to the first set of memory cells at a plurality of adjusted first voltages; and in response to the plurality of first results being all greater than the first preset value, adjust the first set of memory cells to obtain a second set of memory cells, wherein a number of memory cells corresponding to the second set of memory cells is less than a number of memory cells corresponding to the first set of memory cells.
Claim 10
Claims 2-9, 11-13, 15-16, and 18-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 10, and 12 of U.S. Patent No. 12,411609 in view of Applicant Provided Prior Art (APPA) Tokutomi et al. US 2019/0130968.
As per claims 2, 11, and 18, taking claim 2 as exemplary, Tokutomi teaches wherein: the first number of bits comprises a first count of bits that are flipped in the two read results at the first voltage and the first offset voltage ((M2 – M1), para 0163 and FIG. 11, is the number of ON-cells that are newly turned on as a result of the application of the voltages V1 and V2. These are flipped bits compared to their OFF state – See FIG. 11 and the related description);
the second number of bits comprises a second count of bits that are flipped in the two read results at the second voltage and the second offset voltage ((M4 – M3), paras 0164-0165 and FIG. 11, is the number of ON-cells that are newly turned on as a result of the application of the voltages V3 and V4. These are flipped bits compared to their OFF state – See FIG. 11 and the related description).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein: the first number of bits comprises a first count of bits that are flipped in the two read results at the first voltage and the first offset voltage; and the second number of bits comprises a second count of bits that are flipped in the two read results at the second voltage and the second offset voltage”.
As per claims 3 and 12, taking claim 3 as exemplary, Tokutomi teaches wherein the peripheral circuit is configured to: perform, with the first voltage (V1, FIG. 11), the first offset voltage (V2 is greater than V1 by ∆V, FIG. 11), the second voltage (V3, FIG. 11), and the second offset voltage (V4 is greater than V3 by ∆V, FIG. 11), read operations on the first set of memory cells to obtain corresponding read results under a single level read mode (read operation is performed at voltages V1, V2, V3, and V4 – FIG. 11 and related description in paras 0160-0167. Further, two states A and B are shown in FIG.11 which corresponds to a single level read mode).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein the peripheral circuit is configured to: perform, with the first voltage, the first offset voltage, the second voltage, and the second offset voltage, read operations on the first set of memory cells to obtain corresponding read results under a single level read mode”.
As per claims 4, 13, 15, and 19, taking claim 4 as exemplary, Tokutomi teaches wherein the peripheral circuit is configured to: in response to the first result being less than or equal to a first preset value ((M2 – M1) < (M4 – M3) – see the middle drawing of FIG. 11 (number of ON-cells)) and the second result being less than or equal to a second preset value ((M4 – M3) is less than another value of the number of ON-cells, e.g., at voltage VB – see the middle drawing of FIG. 11 (number of ON-cells)), determine a voltage corresponding to a minimum value between the first result and the second result to be the read voltage, wherein the second preset value is lower than the first preset value (based on the change amounts of the number of ON-cells, it is possible to estimate the threshold voltage distribution as shown in the bottom figure of FIG. 11, para 0166).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein the peripheral circuit is configured to: in response to the first result being less than or equal to a first preset value and the second result being less than or equal to a second preset value, determine a voltage corresponding to a minimum value between the first result and the second result to be the read voltage, wherein the second preset value is lower than the first preset value”.
As per claim 5 and 20, taking claim 5 as exemplary, Tokutomi teaches wherein the peripheral circuit is further configured to: in response to the first result being less than or equal to the first preset value, adjust the first voltage with a preset step size to obtain the second voltage (V2 greater than the voltage V1 by ∆V, para 0163 and FIG. 11); wherein: the preset step size is greater than a preset voltage (∆V is greater than 0 – FIG. 11), a first difference between the first voltage and the first offset voltage is less than the preset voltage; and a second difference between the second voltage and the second offset voltage is less than the preset voltage (V4 is greater than V3 by ∆V, para 0165 and FIG. 11).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein the peripheral circuit is further configured to: in response to the first result being less than or equal to the first preset value, adjust the first voltage with a preset step size to obtain the second voltage; wherein: the preset step size is greater than a preset voltage, a first difference between the first voltage and the first offset voltage is less than the preset voltage; and a second difference between the second voltage and the second offset voltage is less than the preset voltage”.
As per dependent claim 6 and 21, taking claim 6 as exemplary, Tokutomi teaches wherein the peripheral circuit is further configured to: in response to the second result being less than the first preset value and greater than the second preset value, adjust the second voltage with the preset step size (V4 is greater than V3 by ∆V, para 0165 and FIG. 11).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein the peripheral circuit is further configured to: in response to the second result being less than the first preset value and greater than the second preset value, adjust the second voltage with the preset step size”.
As per dependent claim 7, 16, and 22, taking claim 7 as exemplary, Tokutomi teaches wherein the peripheral circuit is further configured to: in response to the first result being greater than the first preset value ((M2 – M1) > (M3 – M2), para 0164 and FIG. 11 (bottom drawing)) , perform multiple adjustments to the first voltage, and obtain a plurality of first results respectively corresponding to the first set of memory cells at a plurality of adjusted first voltages (a plurality of voltages V3 and V4 are applied. Correspondingly, a plurality of (M3 – M2) and (M4 – M3) results are obtained – see FIG. 11 and the related description);
in response to the plurality of first results being all greater than the first preset value, adjust the first set of memory cells to obtain a second set of memory cells (See FIG. 5 which shows levels from ER (erase) and A to G. These eight states shown in FIG. 5 correspond to a triple level cell), wherein a number of memory cells corresponding to the second set of memory cells is less than a number of memory cells corresponding to the first set of memory cells (Triple level cell contains fewer number of levels than a quad level cell).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein the peripheral circuit is further configured to: in response to the first result being greater than the first preset value, perform multiple adjustments to the first voltage, and obtain a plurality of first results respectively corresponding to the first set of memory cells at a plurality of adjusted first voltages; and in response to the plurality of first results being all greater than the first preset value, adjust the first set of memory cells to obtain a second set of memory cells, wherein a number of memory cells corresponding to the second set of memory cells is less than a number of memory cells corresponding to the first set of memory cells”.
As per dependent claim 8, Tokutomi teaches wherein the peripheral circuit is further configured to: perform a logical operation on a first read result corresponding to a read operation with the first voltage and a second read result corresponding to a read operation with the first offset voltage, to obtain a first operation result, wherein the first result is obtained based on the first operation result; and perform the logical operation on a third read result corresponding to a read operation with the second voltage and a fourth read result corresponding to a read operation with the second offset voltage, to obtain a second operation result, wherein the second result is obtained based on the second operation result; and wherein the peripheral circuit comprises: a first latch configured to store the first read result and the third read result; a second latch configured to store the second read result and the fourth read result; and a third latch configured to store the first operation result and the second operation result (The latches ADL, BDL, CDL, and DDL temporarily hold read data and write data. The operation unit OP performs various logical operations, such as a NOT operation, an OR operation, an AND operation a NAND operation, a NOR operation, and an XOR operation, on data held in the sense amplifier SA, and the latches ADL, BDL, CDL, DDL and XDL. Para 0117).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein the peripheral circuit is further configured to: perform a logical operation on a first read result corresponding to a read operation with the first voltage and a second read result corresponding to a read operation with the first offset voltage, to obtain a first operation result, wherein the first result is obtained based on the first operation result; and perform the logical operation on a third read result corresponding to a read operation with the second voltage and a fourth read result corresponding to a read operation with the second offset voltage, to obtain a second operation result, wherein the second result is obtained based on the second operation result; and wherein the peripheral circuit comprises: a first latch configured to store the first read result and the third read result; a second latch configured to store the second read result and the fourth read result; and a third latch configured to store the first operation result and the second operation result”.
As per dependent claim 9, Tokutomi teaches wherein: each memory cell of the first set of memory cells is configured to store M bits of data, a read operation with N levels of read voltage is performed on the first set of memory cells to read M type pages of data, each type page corresponds to at least one level of read voltage, the M and the N are both integers greater than 1, and N=2.sup.M−1; and the peripheral circuit is configured to: determine the read voltage corresponding to each level of read voltage at one type of page (see dependent claim 15).
Given the teaching of Tokutomi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the US Patent with “wherein: each memory cell of the first set of memory cells is configured to store M bits of data, a read operation with N levels of read voltage is performed on the first set of memory cells to read M type pages of data, each type page corresponds to at least one level of read voltage, the M and the N are both integers greater than 1, and N=2.sup.M−1; and the peripheral circuit is configured to: determine the read voltage corresponding to each level of read voltage at one type of page”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by APPA Tokutomi et al. US 2019/0130968 (“Tokutomi”).
As per independent claim 1, Tokutomi teaches A memory device (semiconductor storage device 20, para 0081 and FIG. 2), comprising:
an array of memory cells (memory cell array 21, para 0081 and FIG. 2), including a plurality of memory cells (memory cell array 21, para 0081 and FIG. 2);
a peripheral circuit coupled to the array of memory cells (FIG. 2, elements 22-26, para 0081) and configured to:
obtain a first result ((M2 – M1) number of ON-cells, para 0163 and FIG. 11) corresponding to a first set of memory cells (memory cell transistor MT group, para 0161) at a first voltage (V1. M1 is the number of ON-cells and V1 is the voltage of the selected word line WL, paras 0162-0163), wherein the first result includes a first number of bits related to two read results at the first voltage and a first offset voltage (V2. M2 is the number of ON-cells and V2 is the voltage of the selected word line WL, para 0162-0163 and FIG. 11), and the first offset voltage offsets with respect to the first voltage (V2 greater than the voltage V1 by ∆V, para 0163 and FIG. 11);
obtain a second result ((M4 – M3) number of ON-cells, paras 0164-0165 and FIG. 11) corresponding to the first set of memory cells (memory cell transistor MT group, para 0161) at a second voltage adjusted based on the first voltage and the first result (Subsequently, a read operation is performed using a voltage V3 greater than the voltage V2 by ∆V, para 0164 and FIG. 11), wherein the second result includes a second number of bits related to two read results at the second voltage ((M4 – M3) number of ON-cells, paras 0164-0165 and FIG. 11) and a second offset voltage (V4. Subsequently, a read operation is performed using a voltage V4 greater than V3 by ∆V, para 0165 and FIG. 11), and the second offset voltage offsets with respect to the second voltage (V4 is greater than V3 by ∆V, para 0165 and FIG. 11);
determine a read voltage in accordance with the first result and the second result (based on the change amounts of the number of ON-cells, it is possible to estimate the threshold voltage distribution as shown in the bottom figure of FIG. 11, para 0166).
As per dependent claim 2, Tokutomi discloses the device of claim 1. Tokutomi teaches wherein: the first number of bits comprises a first count of bits that are flipped in the two read results at the first voltage and the first offset voltage ((M2 – M1), para 0163 and FIG. 11, is the number of ON-cells that are newly turned on as a result of the application of the voltages V1 and V2. These are flipped bits compared to their OFF state – See FIG. 11 and the related description);
the second number of bits comprises a second count of bits that are flipped in the two read results at the second voltage and the second offset voltage ((M4 – M3), paras 0164-0165 and FIG. 11, is the number of ON-cells that are newly turned on as a result of the application of the voltages V3 and V4. These are flipped bits compared to their OFF state – See FIG. 11 and the related description).
As per dependent claim 3, Tokutomi discloses the device of claim 1. Tokutomi teaches wherein the peripheral circuit is configured to: perform, with the first voltage (V1, FIG. 11), the first offset voltage (V2 is greater than V1 by ∆V, FIG. 11), the second voltage (V3, FIG. 11), and the second offset voltage (V4 is greater than V3 by ∆V, FIG. 11), read operations on the first set of memory cells to obtain corresponding read results under a single level read mode (read operation is performed at voltages V1, V2, V3, and V4 – FIG. 11 and related description in paras 0160-0167. Further, two states A and B are shown in FIG.11 which corresponds to a single level read mode).
As per dependent claim 4, Tokutomi discloses the device of claim 1. Tokutomi teaches wherein the peripheral circuit is configured to: in response to the first result being less than or equal to a first preset value ((M2 – M1) < (M4 – M3) – see the middle drawing of FIG. 11 (number of ON-cells)) and the second result being less than or equal to a second preset value ((M4 – M3) is less than another value of the number of ON-cells, e.g., at voltage VB – see the middle drawing of FIG. 11 (number of ON-cells)), determine a voltage corresponding to a minimum value between the first result and the second result to be the read voltage, wherein the second preset value is lower than the first preset value (based on the change amounts of the number of ON-cells, it is possible to estimate the threshold voltage distribution as shown in the bottom figure of FIG. 11, para 0166. The bottom figure of FIG. 11 shows the minimum value).
As per dependent claim 5, Tokutomi discloses the device of claim 4. Tokutomi teaches wherein the peripheral circuit is further configured to: in response to the first result being less than or equal to the first preset value, adjust the first voltage with a preset step size to obtain the second voltage (V2 greater than the voltage V1 by ∆V, para 0163 and FIG. 11); wherein: the preset step size is greater than a preset voltage (∆V is greater than 0 – FIG. 11), a first difference between the first voltage and the first offset voltage is less than the preset voltage; and a second difference between the second voltage and the second offset voltage is less than the preset voltage (V4 is greater than V3 by ∆V, para 0165 and FIG. 11).
As per dependent claim 6, Tokutomi discloses the device of claim 5. Tokutomi teaches wherein the peripheral circuit is further configured to: in response to the second result being less than the first preset value and greater than the second preset value, adjust the second voltage with the preset step size (V4 is greater than V3 by ∆V, para 0165 and FIG. 11).
As per dependent claim 7, Tokutomi discloses the device of claim 4. Tokutomi teaches wherein the peripheral circuit is further configured to: in response to the first result being greater than the first preset value ((M2 – M1) > (M3 – M2), para 0164 and FIG. 11 (bottom drawing)) , perform multiple adjustments to the first voltage, and obtain a plurality of first results respectively corresponding to the first set of memory cells at a plurality of adjusted first voltages (a plurality of voltages V3 and V4 are applied. Correspondingly, a plurality of (M3 – M2) and (M4 – M3) results are obtained – see FIG. 11 and the related description);
in response to the plurality of first results being all greater than the first preset value, adjust the first set of memory cells to obtain a second set of memory cells (See FIG. 5 which shows levels from ER (erase) and A to G. These eight levels shown in FIG. 5 correspond to a triple level cell), wherein a number of memory cells corresponding to the second set of memory cells is less than a number of memory cells corresponding to the first set of memory cells (Triple level cell contains fewer number of levels than a quad level cell).
As per dependent claim 8, Tokutomi discloses the device of claim 1. Tokutomi teaches wherein the peripheral circuit is further configured to: perform a logical operation on a first read result corresponding to a read operation with the first voltage and a second read result corresponding to a read operation with the first offset voltage, to obtain a first operation result, wherein the first result is obtained based on the first operation result; and perform the logical operation on a third read result corresponding to a read operation with the second voltage and a fourth read result corresponding to a read operation with the second offset voltage, to obtain a second operation result, wherein the second result is obtained based on the second operation result; and wherein the peripheral circuit comprises: a first latch configured to store the first read result and the third read result; a second latch configured to store the second read result and the fourth read result; and a third latch configured to store the first operation result and the second operation result (The latches ADL, BDL, CDL, and DDL temporarily hold read data and write data. The operation unit OP performs various logical operations, such as a NOT operation, an OR operation, an AND operation a NAND operation, a NOR operation, and an XOR operation, on data held in the sense amplifier SA, and the latches ADL, BDL, CDL, DDL and XDL. Para 0117).
As per dependent claim 9, Tokutomi discloses the device of claim 1. Tokutomi teaches wherein: each memory cell of the first set of memory cells is configured to store M bits of data, a read operation with N levels of read voltage is performed on the first set of memory cells to read M type pages of data, each type page corresponds to at least one level of read voltage, the M and the N are both integers greater than 1, and N=2.sup.M−1; and the peripheral circuit is configured to: determine the read voltage corresponding to each level of read voltage at one type of page (see dependent claim 15).
As per claims 10-13, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-4. See FIG. 1 of Tokutomi for a memory system 1 including controller 10, para 0068.
As per claims 14-16, these claims are respectively rejected based on arguments provided above for similar rejected claims 1, 4, and 7.
As per claims 17-22, these claims are respectively rejected based on arguments provided above for similar rejected claims 1-2 and 4-7. See FIG. 1 of Tokutomi for a memory system 1 including controller 10, para 0068.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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