DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Specification
The disclosure is objected to because of the following informalities: paragraph [0001], line 3, --now U.S. Patent No. 12,431,890 issued on Sept. 30, 2025,-- should be inserted before “which,”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The newly added limitation “wherein the symmetrical arrangement is configured to substantially equalize an effective capacitance of the integrated circuit as measured from the first terminal versus as measured from the second terminal.” (emphasis added) is not described in the application as originally filed. At the time of filing, this recited feature in the above limitation were not defined as a critical feature of the present invention. Therefore, this limitation in the claims is seen as new matter. Applicant is required to cancel the new matter in the reply to this Office action.
Claim 14 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The newly added limitation “wherein the symmetrical arrangement is configured to improve at least one of a differential linearity or an integral linearity of the DTC when driven from either the first terminal or the second terminal.” (emphasis added) is not described in the application as originally filed. At the time of filing, this recited feature in the above limitation were not defined as a critical feature of the present invention. Therefore, this limitation in the claims is seen as new matter. Applicant is required to cancel the new matter in the reply to this Office action.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The newly added limitation “wherein the symmetrical physical arrangement is configured to improve a linearity of the integrated circuit when driven from either the first terminal or the second terminal.” (emphasis added) is not described in the application as originally filed. At the time of filing, this recited feature in the above limitation were not defined as a critical feature of the present invention. Therefore, this limitation in the claims is seen as new matter. Applicant is required to cancel the new matter in the reply to this Office action.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The newly added limitation “wherein the symmetrical physical arrangement is configured to make a capacitance versus state curve of the integrated circuit substantially monotonic when driven from either the first terminal or the second terminal” (emphasis added) is not described in the application as originally filed. At the time of filing, this recited feature in the above limitation were not defined as a critical feature of the present invention. Therefore, this limitation in the claims is seen as new matter. Applicant is required to cancel the new matter in the reply to this Office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1 and 4-7 of U.S. Patent No. 12,431,890. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6 of U.S. Patent No. 12,431,890. Claim 6 of U.S. Patent No. 12,431,890, by virtue of its dependency from claim 1, recites an integrated circuit comprising a series arrangement of three or more field-effect transistors (FETs), wherein the FETs are configured to be connected in series with a series arrangement of one or more capacitive elements, and wherein a combination of the one or more capacitive elements and the FETs is coupled between a first node and a second node. Claim 6 further requires that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. The subject matter of present claim 2 differs from the subject matter of claim 6 of U.S. Patent No. 12,431,890 in expressly reciting that the plurality of switches defines a series path having a central point and that the at least one capacitive element is physically placed in a symmetrical arrangement with respect to the central point of the plurality of switches. However, the subject matter of claim 2 is not patentably distinct from the subject matter of claim 6 of U.S. Patent No. 12,431,890. The reference claim already requires a series arrangement of FET switches and capacitive elements between first and second nodes and further requires a symmetrical capacitive relationship with reference to a node within the integrated circuit. Providing the capacitive element in a physically symmetrical arrangement with respect to a central point of the series-connected FETs would have been an obvious implementation of the symmetrical capacitive arrangement recited in the reference claim, particularly where the physical arrangement merely implements the claimed symmetrical electrical relationship in the series-connected circuit. Accordingly, claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6 of U.S. Patent No. 12,431,890.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, in view of claim 1 from which claim 6 depends, of U.S. Patent No. 12,431,890.
As discussed above with respect to Claim 2, claim 6 of U.S. Patent No. 12,431,890, by virtue of its dependency from claim 1, recites an integrated circuit comprising a series arrangement of three or more field-effect transistors (FETs), wherein the FETs are configured to be connected in series with a series arrangement of one or more capacitive elements, and wherein a combination of the one or more capacitive elements and the FETs is coupled between a first node and a second node. Claim 6 further requires that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. Claim 3 depends from Claim 2 and further recites that “the symmetrical arrangement comprises a single capacitive element of the at least one capacitive element being placed in a middle position of the series path defined by the plurality of switches.”
The subject matter of Claim 3 is not patentably distinct from the subject matter of claim 6 of U.S. Patent No. 12,431,890. The reference claims already require a series arrangement comprising a plurality of FET switches and one or more capacitive elements and further require a symmetrical capacitive relationship with reference to a node within the integrated circuit. With respect to the additional limitation requiring a single capacitive element to be placed in a middle position of the series path, positioning a single series capacitive element at the middle of the series-connected switch arrangement would have been an obvious implementation of the symmetrical capacitive arrangement encompassed by the reference claims. In particular, positioning the capacitive element at the middle of the switch stack provides symmetry about the capacitive element such that corresponding portions of the switch stack are disposed on opposite sides thereof, thereby providing the predictable symmetrical relationship contemplated by the reference claims. Accordingly, Claim 3 does not define a patentably distinct invention merely by specifying that the symmetrical arrangement comprises a single capacitive element positioned in the middle of the series path defined by the plurality of switches. Therefore, Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, in view of claim 1 from which claim 6 depends, of U.S. Patent No. 12,431,890.
Claims 4 and 5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, in view of claim 1 from which claim 6 depends, of U.S. Patent No. 12,431,890.
As discussed above with respect to Claim 2, claim 6 of U.S. Patent No. 12,431,890, by virtue of its dependency from claim 1, recites an integrated circuit comprising a series arrangement of three or more field-effect transistors (FETs), wherein the FETs are configured to be connected in series with a series arrangement of one or more capacitive elements, and wherein a combination of the one or more capacitive elements and the FETs is coupled between a first node and a second node. Claim 6 further requires that compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit.
With regard to Claim 4, Claim 4 depends from Claim 2 and further recites that the symmetrical arrangement comprises a first capacitive element placed at a first end of the series path adjacent to the first terminal and a second capacitive element placed at a second end of the series path adjacent to the second terminal. The subject matter of Claim 4 is not patentably distinct from the subject matter of claim 6 of U.S. Patent No. 12,431,890. The reference claims already require a series arrangement comprising a plurality of FET switches and one or more capacitive elements between first and second nodes and further require a symmetrical capacitive relationship with reference to a node within the integrated circuit. Providing first and second capacitive elements at corresponding opposite ends of the series path, with the first capacitive element adjacent to the first terminal and the second capacitive element adjacent to the second terminal, would have been an obvious implementation of the symmetrical capacitive arrangement encompassed by the reference claims. Placement of corresponding capacitive elements at opposite ends of the series path provides a predictable symmetrical arrangement with respect to the switch stack and preserves substantially corresponding circuit characteristics when viewed from either terminal. Accordingly, specifying that the symmetrical arrangement comprises first and second capacitive elements positioned at respective opposite ends of the series path does not render Claim 4 patentably distinct from claim 6 of U.S. Patent No. 12,431,890.
With regard to Claim 5, Claim 5 depends from Claim 4 and further recites that “a capacitance value of the first capacitive element is substantially equal to a capacitance value of the second capacitive element.” The subject matter of Claim 5 is likewise not patentably distinct from the subject matter of claim 6 of U.S. Patent No. 12,431,890. Claim 6 expressly requires that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. Providing substantially equal capacitance values for corresponding capacitive elements positioned at opposite ends of the series path would have been an obvious implementation of the symmetrical capacitive relationship recited by the reference claim because substantially equal capacitance values at corresponding symmetrical positions provide the predictable result of maintaining electrical symmetry between opposite portions of the circuit. Therefore, Claims 4 and 5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, in view of claim 1 from which claim 6 depends, of U.S. Patent No. 12,431,890.
With regard to Claim 6, Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, in view of claim 1 from which claim 6 depends, of U.S. Patent No. 12,431,890.
As discussed above with respect to Claim 2, Claim 6 of U.S. Patent No. 12,431,890, by virtue of its dependency from Claim 1, recites an integrated circuit comprising a series arrangement of three or more field-effect transistors (FETs), wherein the FETs are configured to be connected in series with a series arrangement of one or more capacitive elements, and wherein a combination of the one or more capacitive elements and the FETs is coupled between a first node and a second node. Claim 6 further requires that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. Claim 6 further recites that “the symmetrical arrangement comprises a first capacitive element placed at a first intermediate position within the series path and a second capacitive element placed at a second intermediate position within the series path, wherein the first and second intermediate positions are symmetrical with respect to the central point.” The subject matter of Claim 6 is not patentably distinct from the subject matter of claim 6 of U.S. Patent No. 12,431,890. The reference claims already require a series arrangement comprising a plurality of FET switches and capacitive elements and further require a symmetrical capacitive relationship with reference to a node within the integrated circuit. Providing first and second capacitive elements at respective intermediate positions on opposite sides of the central point of the series path would have been an obvious implementation of the symmetrical capacitive arrangement encompassed by the reference claims. In particular, positioning the first and second capacitive elements at corresponding intermediate positions that are symmetrical with respect to the central point predictably provides corresponding capacitive relationships on opposite portions of the switch stack and thereby maintains the symmetrical relationship required by the reference claims. Accordingly, merely specifying that the first and second capacitive elements are positioned at corresponding intermediate locations on opposite sides of the central point of the series path does not render the subject matter of Claim 6 patentably distinct from the subject matter of claim 6 of U.S. Patent No. 12,431,890. Therefore, Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, in view of claim 1 from which claim 6 depends, of U.S. Patent No. 12,431,890.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 1 of U.S. Patent No. 12,431,890. Although the claim at issue are not identical, they are not patentably distinct from each other because the limitation "wherein the plurality of switches comprises a plurality of field-effect transistors.", as recited in Claim 7 of the present application, is clearly rendered obvious by the claimed limitation “a series arrangement of three or more field-effect transistors (FET)” of Claim 1 of U.S. Patent No. 12,431,890.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 4 and 5 of U.S. Patent No. 12,431,890. Although the claim at issue are not identical, they are not patentably distinct from each other because the limitation "wherein the at least one capacitive element is a metal-insulator-metal capacitor or a metal-metal capacitor.", as recited in Claim 8 of the present application, is clearly rendered obvious by the claimed limitation “wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors.” of Claims 4 and 5 of U.S. Patent No. 12,431,890.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
With regard to Claim 9, Claim 9 depends from Claim 2 and therefore includes all of the limitations of Claim 2, including a first terminal and a second terminal; a plurality of switches connected in series between the first and second terminals and defining a series path having a central point; and at least one capacitive element connected in series with the plurality of switches along the series path and physically placed in a symmetrical arrangement with respect to the central point of the plurality of switches. The claims of U.S. Patent No. 12,431,890 recite corresponding subject matter directed to an integrated circuit having a series arrangement of field-effect transistors and one or more capacitive elements arranged along the series path. Claim 9 further recites that “the symmetrical arrangement is configured to substantially equalize an effective capacitance of the integrated circuit as measured from the first terminal versus as measured from the second terminal.” The additional limitation of Claim 9 does not render the claimed subject matter patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. In particular, given the symmetrical arrangement of the capacitive element or elements with respect to the central point of the series-connected switching arrangement, substantially equalizing the effective capacitance as viewed from opposite terminals would have been an expected result of such symmetrical placement. One of ordinary skill in the art would have recognized that symmetrically arranging the capacitive elements relative to the central point of the series path provides substantially corresponding electrical characteristics when the circuit is viewed from either terminal, including substantially equal effective capacitance. Accordingly, Claim 9 is not patentably distinct from the claims of U.S. Patent No. 12,431,890 and is therefore rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
With regard to Claim 10, Claim 10 depends from Claim 2 and therefore includes all of the limitations of Claim 2, including a first terminal and a second terminal; a plurality of switches connected in series between the first terminal and the second terminal, the plurality of switches defining a series path having a central point; and at least one capacitive element connected in series with the plurality of switches along the series path and physically placed in a symmetrical arrangement with respect to the central point of the plurality of switches. Claim 10 further recites “a plurality of compensation capacitors, each compensation capacitor coupled in parallel with a respective switch of the plurality of switches.” The claims of U.S. Patent No. 12,431,890 recite corresponding subject matter including a series arrangement of field-effect transistors (FETs) and compensation capacitive elements coupled in parallel with respective FETs of the series arrangement. Thus, the claims of U.S. Patent No. 12,431,890 teach the use of compensation capacitors coupled in parallel with the respective switching devices of a series-connected switching arrangement. Accordingly, the additional limitation of Claim 10 requiring a plurality of compensation capacitors, each compensation capacitor being coupled in parallel with a respective switch of the plurality of switches, does not patentably distinguish the claimed subject matter from the subject matter claimed in U.S. Patent No. 12,431,890. One of ordinary skill in the art would have found it obvious to provide the series-connected switches of Claim 2 with respective compensation capacitors coupled in parallel therewith, as claimed in U.S. Patent No. 12,431,890, thereby obtaining the corresponding compensation of the electrical characteristics of the respective switches. Therefore, Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7, in view of claims 6 and 1 from which claim 7 ultimately depends, of U.S. Patent No. 12,431,890. Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons set forth below. Claim 7 of U.S. Patent No. 12,431,890 recites a digitally tuned capacitor (DTC) comprising a plurality of the integrated circuits of claim 6, wherein the plurality of integrated circuits are configured in parallel. Claim 6 depends from claim 1 and further requires that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. Claim 1 recites an integrated circuit comprising a series arrangement of three or more field-effect transistors (FETs), wherein the three or more FETs are configured to be connected in series with a series arrangement of one or more capacitive elements, and wherein a combination of the one or more capacitive elements and the three or more FETs is coupled between a first node and a second node. Accordingly, claim 7, by virtue of its dependency from claims 6 and 1, claims a digitally tuned capacitor comprising a plurality of integrated circuits configured in parallel, each integrated circuit comprising a plurality of series-connected FET switches and one or more capacitive elements connected in series therewith between first and second nodes, with a symmetrical capacitive relationship referenced to a node within the integrated circuit. Present claim 11 differs from claim 7 of U.S. Patent No. 12,431,890 principally in expressly reciting that the plurality of switches defines a series path having a “central point,” that the at least one capacitive element is “physically placed in a symmetrical arrangement with respect to the central point of the plurality of switches,” and that the symmetrical arrangement is “to improve bi-directionality of the unit cell.” However, these differences do not render present claim 11 patentably distinct from claim 7 of U.S. Patent No. 12,431,890. The series arrangement of FETs and capacitive elements recited by claims 1, 6, and 7 of U.S. Patent No. 12,431,890 establishes a series path between first and second nodes, and claim 6 expressly requires a symmetrical capacitive relationship with reference to a node within the integrated circuit. The reference patent further makes clear, in construing the scope and utility of the claimed arrangement, that the symmetrical capacitive arrangement is directed to improving the bi-directionality of stacked elements connected between terminals. Therefore, physically arranging the series-connected capacitive element symmetrically with respect to a central point of the series-connected switches represents an obvious physical implementation of the symmetrical capacitive arrangement encompassed by the reference claims. Such an arrangement would predictably provide substantially symmetrical circuit behavior when the circuit is driven from either terminal and thereby improve bi-directionality. Furthermore, the recitation “to improve bi-directionality of the unit cell” does not distinguish the claimed DTC from the DTC of claim 7 of U.S. Patent No. 12,431,890 because the recitation describes the intended function or result of the claimed symmetrical arrangement rather than requiring an additional structural distinction. The reference claims already recite the underlying DTC structure comprising parallel integrated circuits having series-connected FETs and capacitive elements together with a symmetrical capacitive relationship relative to an internal node. Accordingly, claim 11 is not patentably distinct from claim 7, in view of claims 6 and 1 from which claim 7 ultimately depends, of U.S. Patent No. 12,431,890.
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890. With regard to Claim 12, Claim 12 depends from Claim 11 and further recites that “the symmetrical arrangement comprises a single capacitive element placed in a middle position of the series path.” As discussed above with respect to Claim 11, the claimed DTC comprising a plurality of switches connected in series and at least one capacitive element arranged along the series path is not patentably distinct from the corresponding integrated-circuit subject matter claimed in U.S. Patent No. 12,431,890. With respect to the additional limitation of Claim 12, U.S. Patent No. 12,431,890 discloses an embodiment in which a single MIM or MM capacitor is placed in the middle of the FET stack. Such placement provides a symmetrical arrangement in which the parasitic capacitances are symmetric about the capacitor, such that the electrical characteristics of the RF+ and RF− sides mirror one another. Accordingly, it would have been obvious to one of ordinary skill in the art to configure the capacitive element of the claimed DTC at a middle position of the series path, as taught by U.S. Patent No. 12,431,890, in order to provide a symmetrical arrangement with respect to the series-connected switching devices and thereby reduce or eliminate capacitance asymmetry between the opposite ends of the DTC. Therefore, the additional limitation of Claim 12 does not render the claimed subject matter patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. Accordingly, Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
With regard to Claim 13, Claim 13 depends from Claim 11 and further recites that “the symmetrical arrangement comprises a first capacitive element placed at a first end of the series path and a second capacitive element placed at a second end of the series path.” As discussed above with respect to Claim 11, the claimed DTC comprising a plurality of switchable unit cells, each including a plurality of switches connected in series with at least one capacitive element along a series path, is not patentably distinct from the corresponding integrated-circuit and DTC subject matter claimed in U.S. Patent No. 12,431,890. U.S. Patent No. 12,431,890 further teaches symmetrical arrangements of capacitive elements with respect to the series-connected switching devices. In particular, the patent describes an embodiment in which MIM capacitors are placed at both ends of the FET stack, thereby providing a symmetrical configuration. The patent explains that MIM capacitors may be placed in various positions provided that they are symmetrical with respect to the center of the stack, including an arrangement having one capacitive element at each end of the stack. Accordingly, it would have been obvious to one of ordinary skill in the art to implement the symmetrical capacitive arrangement of the DTC by placing a first capacitive element at a first end of the series path and a second capacitive element at a second end of the series path, thereby providing the symmetrical arrangement taught by U.S. Patent No. 12,431,890 and reducing capacitance asymmetry between the opposite ends of the DTC. Therefore, the additional limitation of Claim 13 does not render the claimed subject matter patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. Accordingly, Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
With regard to Claim 14, Claim 14 depends from Claim 11 and further recites that “the symmetrical arrangement is configured to improve at least one of a differential linearity or an integral linearity of the DTC when driven from either the first terminal or the second terminal.” As discussed above with respect to Claim 11, the claimed DTC comprising a plurality of switches and at least one capacitive element arranged symmetrically along the series path is not patentably distinct from the corresponding integrated-circuit and DTC subject matter claimed in U.S. Patent No. 12,431,890. In particular, Claim 6 of U.S. Patent No. 12,431,890 recites compensation capacitive elements providing capacitance values that are symmetrical with reference to a node within the integrated circuit, and Claim 7 recites a digitally tuned capacitor (DTC) comprising a plurality of the integrated circuits of Claim 6 configured in parallel. With respect to the additional limitation of Claim 14, U.S. Patent No. 12,431,890 teaches that an asymmetric capacitive arrangement produces different electrical characteristics depending upon whether the DTC is driven from the RF+ terminal or the RF− terminal. The patent particularly identifies differences in differential nonlinearity (DNL) and integral nonlinearity (INL) resulting from the asymmetric arrangement and explains that, ideally, both DNL and INL should approach zero across the various capacitance states. U.S. Patent No. 12,431,890 further teaches that symmetrically positioning the capacitive elements with respect to the FET stack reduces or eliminates the capacitance asymmetry between the RF+ and RF− driving conditions and expressly reports an improvement in DNL resulting from the symmetrical arrangement. Accordingly, one of ordinary skill in the art would have found it obvious to employ the symmetrical capacitance arrangement claimed in U.S. Patent No. 12,431,890 in the DTC in order to improve the differential linearity and/or integral linearity of the DTC when driven from either terminal. The recited improvement in differential linearity or integral linearity therefore does not render Claim 14 patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. Therefore, Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 6 and 7 of U.S. Patent No. 12,431,890.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 6 and 7 of U.S. Patent No. 12,431,890. Although the claim at issue are not identical, they are not patentably distinct from each other because the limitation "wherein the plurality of switches comprises a plurality of field-effect transistors.", as recited in Claim 15 of the present application, is clearly rendered obvious by the claimed limitation “a series arrangement of three or more field-effect transistors (FET)” of Claim 1 of U.S. Patent No. 12,431,890; and the limitation "wherein the at least one capacitive element is a metal-insulator-metal capacitor", as recited in Claim 15 of the present application, is clearly rendered obvious by the claimed limitation “the at least one capacitive element is a metal-insulator-metal capacitor” of Claim 4 of U.S. Patent No. 12,431,890.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
With regard to Claim 16, although Claim 16 is directed to a method for fabricating a bi-directional integrated circuit, the limitations of Claim 16 substantially correspond to the structural limitations of the integrated circuit recited in Claim 2. In particular, Claim 16 recites forming a plurality of switches connected in a series path between a first terminal and a second terminal, the series path having a central point, and forming at least one capacitive element in the series path with the plurality of switches, wherein the capacitive element is placed in a symmetrical physical arrangement with respect to the central point of the series path. These limitations correspond to the integrated-circuit structure recited in Claim 2, namely, a first terminal and a second terminal, a plurality of switches connected in series between the first and second terminals and defining a series path having a central point, and at least one capacitive element connected in series with the plurality of switches along the series path and physically placed in a symmetrical arrangement with respect to the central point of the plurality of switches. Claim 16 further recites that the symmetrical physical arrangement is provided “to substantially balance parasitic capacitances as seen from the first terminal and the second terminal.” This limitation represents the electrical result or function obtained from the symmetrical physical arrangement of the capacitive element with respect to the central point of the series path. The symmetrical arrangement provides substantially corresponding electrical characteristics as viewed from opposite ends of the series path and thereby substantially balances the parasitic capacitances as seen from the first and second terminals. Although Claim 16 is presented in method form, the recited fabrication steps amount to forming the structural arrangement that is not patentably distinct from the integrated-circuit subject matter claimed in U.S. Patent No. 12,431,890. The mere recitation of forming the respective structural elements does not render the claimed method patentably distinct where the method merely requires fabrication of the corresponding claimed integrated-circuit structure. It would have been obvious to one of ordinary skill in the art to fabricate the integrated circuit claimed in U.S. Patent No. 12,431,890 by forming its recited switches and capacitive elements in their claimed physical arrangement. Such fabrication necessarily or predictably results in the corresponding integrated-circuit structure, including the electrical characteristics resulting from the symmetrical physical arrangement. Accordingly, the subject matter of Claim 16 is not patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. Therefore, Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Furthermore, Claims 17-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890. The limitations of Claims 17-19 substantially correspond to the structural limitations of the integrated circuit recited in Claims 3, 4, 7 and 8, respectively.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Claim 20 depends from Claim 16 and further recites that “the symmetrical physical arrangement is configured to improve a linearity of the integrated circuit when driven from either the first terminal or the second terminal.” As discussed above with respect to Claim 16, the method limitations directed to forming the series-connected switches and capacitive elements in a symmetrical physical arrangement are not patentably distinct from the corresponding integrated-circuit subject matter claimed in U.S. Patent No. 12,431,890. In particular, Claim 6 of U.S. Patent No. 12,431,890, through its dependency from Claim 1, recites an integrated circuit comprising a series arrangement of FETs and capacitive elements and further recites that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. Although Claim 6 of U.S. Patent No. 12,431,890 does not expressly recite improving linearity when the circuit is driven from either terminal, such improved bidirectional linearity would have been an obvious electrical consequence of providing the claimed symmetrical capacitance arrangement. U.S. Patent No. 12,431,890 explains that an asymmetric arrangement produces different electrical characteristics depending upon whether the RF+ or RF− terminal is driven, including differences in differential nonlinearity (DNL) and integral nonlinearity (INL), whereas symmetrical placement of the capacitive elements eliminates or reduces such asymmetry and provides corresponding electrical behavior when driven from either terminal. Accordingly, one of ordinary skill in the art, considering the subject matter claimed in Claim 6 of U.S. Patent No. 12,431,890 as a whole, would have found it obvious to employ the claimed symmetrical capacitance arrangement to improve the linearity of the integrated circuit when driven from either the first terminal or the second terminal. The recited improvement in linearity therefore does not render Claim 20 patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. Therefore, Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 6 of U.S. Patent No. 12,431,890.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,431,890.
Claim 21 depends from Claim 16 and further recites that “the symmetrical physical arrangement is configured to make a capacitance versus state curve of the integrated circuit substantially monotonic when driven from either the first terminal or the second terminal.” As discussed above with respect to Claim 16, the method limitations directed to forming the series-connected switches and capacitive elements in a symmetrical physical arrangement are not patentably distinct from the corresponding integrated-circuit subject matter claimed in U.S. Patent No. 12,431,890. In particular, Claim 6 of U.S. Patent No. 12,431,890, through its dependency from Claim 1, recites an integrated circuit comprising a series arrangement of FETs and capacitive elements and further recites that the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit. Although Claim 6 of U.S. Patent No. 12,431,890 does not expressly recite a substantially monotonic capacitance-versus-state curve, such a characteristic would have been an obvious electrical consequence of providing the claimed symmetrical capacitance arrangement. U.S. Patent No. 12,431,890 explains that an asymmetric arrangement can result in non-monotonic capacitance values depending upon which terminal is driven, whereas symmetrical placement of the capacitive elements about the stack eliminates capacitance asymmetry and provides corresponding capacitance characteristics when the integrated circuit is driven from either terminal. Accordingly, one of ordinary skill in the art, considering the subject matter claimed in Claim 6 of U.S. Patent No. 12,431,890 as a whole, would have found it obvious to employ the claimed symmetrical capacitance arrangement to provide a substantially monotonic capacitance-versus-state characteristic when the integrated circuit is driven from either the first terminal or the second terminal. The recited substantially monotonic capacitance-versus-state characteristic therefore does not render Claim 21 patentably distinct from the subject matter claimed in U.S. Patent No. 12,431,890. Therefore, Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 6 of U.S. Patent No. 12,431,890.
Reference of Note
The prior art of Record and not relied upon is considered pertinent to applicant’s disclosure: Ranta (US 9,024,700) teaches a method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device.
Conclusion
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/HAI L NGUYEN/Primary Examiner, Art Unit 2836 September 19, 2026
