Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows: The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed applications, Application No’s. 18/628,357, 18/322,104, 17/955,188 and 17/202,704, fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
Claim 2 and analogous claim 12 recites, “wherein the controller is further configured to: determine, based on the second ratio, whether to suspend one of the plurality of the second commands, which is being executed in the nonvolatile memory”. However, the specification only ever discloses suspending a command based on the cumulative weight, VT [pg. 5] [pgs. 28-29]. Furthermore, rather than being “based on the second ratio”, the specification discloses that the desired effect of suspending a command is to suppress the variation in the amount of read latency below a threshold value rather than to control the second ratio or be based on “the second ratio” [pg. 28]. Accordingly, the limitation is not supported by the prior-filed applications.
Claims 3-4 and 13-14 also do not have adequate support in the prior-filed applications at least by virtue of their dependence from claims 2 and 12.
Applicant’s claim for priority under 35 USC §119(a) to Japanese Application No. JP2020-140065 is acknowledged. However, claims 2-4 and 12-14 are not entitled to priority to the filing date of the Japanese Application because the Japanese Application does not provide adequate written description support under 35 USC §112(a) for the claims.
The Japanese Application does not provide support for “wherein the controller is further configured to: determine, based on the second ratio, whether to suspend one of the plurality of the second commands, which is being executed in the nonvolatile memory” according to a similar analysis as that performed above with regards to the parent applications of the instant application. Accordingly, the effective filing date of claims 2-4 and 12-14 is no earlier than 04 December 2025 and they are not entitled to the priority of the Japanese Application or continuation claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 5-11 and 15-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12,411,638 B2 in view of US Patent Application Publication US 2019/0265888 A1 (Yang).
Instant Application
‘638
Yang
1. A memory system connectable to a host, the memory system comprising:
a nonvolatile memory that includes a plurality of memory dies;
and a controller electrically connected to the nonvolatile memory via a plurality of channels and configured to:
manage a first execution period of a first command, the first execution period being a period in which the first command is executed in the nonvolatile memory;
manage a second execution period of a second command, the second execution period being a period in which the second command is executed in the nonvolatile memory, the second execution period being longer than the first execution period;
and in response to receiving a first ratio from the host, schedule a plurality of the first commands and a plurality of the second commands to be executed in the nonvolatile memory such that a second ratio matches with the first ratio, wherein the second ratio is a ratio of a first total period to a second total period, the first total period being a total of the first execution period of each of the plurality of the first commands, and the second total period being a total of the second execution period of each of the plurality of the second commands.
1. A memory system connectable to a host, the memory system comprising:
a nonvolatile memory;
and a controller electrically connected to the nonvolatile memory and configured to:
manage a first execution period of a first command, the first execution period being a period in which the first command is executed in the nonvolatile memory;
manage a second execution period of a second command, the second execution period being a period in which the second command is executed in the nonvolatile memory, the second execution period being longer than the first execution period;
and in response to receiving a first ratio from the host, schedule a plurality of the first commands and a plurality of the second commands to be executed in the nonvolatile memory such that a second ratio matches with the first ratio, wherein the second ratio is a ratio of a first total period to a second total period, the first total period being a total of the first execution period of each of the plurality of the first commands, and the second total period being a total of the second execution period of each of the plurality of the second commands.
“some storage systems… operate on multiple memory dies via different channels in parallel to enhance the system’s sequential write performance” [0002]. Where the different channels are connected between the non-volatile memory die and the controller [0043].
5. The memory system according to claim 1, wherein the controller includes a first queue for queuing the plurality of the first commands, and the controller is further configured to: determine, based on the first and second execution periods and the first ratio, a first upper limit of the number of the first commands to be queued in the first queue.
2. The memory system according to claim 1, wherein the controller includes a first queue for queuing the plurality of the first commands, and the controller is further configured to: determine, based on the first and second execution periods and the first ratio, a first upper limit of the number of the first commands to be queued in the first queue.
6. The memory system according to claim 5, wherein the controller is configured to: determine the first upper limit such that the second ratio matches with the first ratio.
3. The memory system according to claim 2, wherein the controller is configured to: determine the first upper limit such that the second ratio matches with the first ratio.
4. The memory system according to claim 1, wherein the controller is further configured to: manage a cumulative weight; in response to one of the plurality of the first commands starting to be executed in the nonvolatile memory, update the cumulative weight by executing a first operation that includes one of an addition operation or a subtraction operation to the cumulative weight; in response to one of the plurality of the second commands starting to be executed in the nonvolatile memory, update the cumulative weight by executing a second operation that is the other of the addition operation or the subtraction operation from the first operation to the cumulative weight; and determine, based on whether or not the cumulative weight is larger than a threshold value, which of the first and second commands to be executed next in the nonvolatile memory.
4. The memory system according to claim 1, wherein the controller is further configured to: manage a cumulative weight; in response to one of the plurality of the first commands starting to be executed in the nonvolatile memory, update the cumulative weight by executing a first operation that includes one of an addition operation or a subtraction operation to the cumulative weight; in response to one of the plurality of the second commands starting to be executed in the nonvolatile memory, update the cumulative weight by executing a second operation that is the other of the addition operation or the subtraction operation from the first operation to the cumulative weight; and determine, based on whether or not the cumulative weight is larger than a threshold value, which of the first and second commands to be executed next in the nonvolatile memory.
8. The memory system according to claim 7, wherein the first operation is the subtraction operation and the second operation is the addition operation, and the controller is configured to: in response to the one of the plurality of the first commands starting to be executed in the nonvolatile memory, update the cumulative weight by subtracting a first value from the cumulative weight, the first value being a value corresponding to the first execution period; in response to the one of the plurality of the second commands starting to be executed in the nonvolatile memory, update the cumulative weight by adding a second value to the cumulative weight, the second value being larger than the first value and being a value corresponding to the second execution period; and in response to the cumulative weight being larger than the threshold value, determine the first command to be executed next in the nonvolatile memory.
5. The memory system according to claim 4, wherein the first operation is the subtraction operation and the second operation is the addition operation, and the controller is configured to: in response to the one of the plurality of the first commands starting to be executed in the nonvolatile memory, update the cumulative weight by subtracting a first value from the cumulative weight, the first value being a value corresponding to the first execution period; in response to the one of the plurality of the second commands starting to be executed in the nonvolatile memory, update the cumulative weight by adding a second value to the cumulative weight, the second value being larger than the first value and being a value corresponding to the second execution period; and in response to the cumulative weight being larger than the threshold value, determine the first command to be executed next in the nonvolatile memory.
9. The memory system according to claim 7, wherein the controller is further configured to: determine, based on whether or not the cumulative weight is larger than the threshold value, whether to suspend the one of the plurality of the second commands, which is being executed in the nonvolatile memory.
6. The memory system according to claim 4, wherein the controller is further configured to: determine, based on whether or not the cumulative weight is larger than the threshold value, whether to suspend the one of the plurality of the second commands, which is being executed in the nonvolatile memory.
10. The memory system according to claim 1, where the first command is a read command and the second command is a program command or an erase command.
7. The memory system according to claim 1, wherein the first command is a read command and the second command is a program command or an erase command.
11. A method of controlling a nonvolatile memory that includes a plurality of memory dies, the method comprising: communicating with the nonvolatile memory via a plurality of channels;
managing a first execution period of a first command, the first execution period being a period in which the first command is executed in the nonvolatile memory;
managing a second execution period of a second command, the second execution period being a period in which the second command is executed in the nonvolatile memory, the second execution period being longer than the first execution period;
receiving a first ratio from a host; and in response to receiving the first ratio, scheduling a plurality of the first commands and a plurality of the second commands to be executed in the nonvolatile memory such that a second ratio matches with the first ratio, wherein the second ratio is a ratio of a first total period to a second total period, the first total period being a total of the first execution period of each of the plurality of the first commands, and the second total period being a total of the second execution period of each of the plurality of the second commands.
8. A method of controlling a nonvolatile memory, comprising:
managing a first execution period of a first command, the first execution period being a period in which the first command is executed in the nonvolatile memory;
managing a second execution period of a second command, the second execution period being a period in which the second command is executed in the nonvolatile memory, the second execution period being longer than the first execution period;
receiving a first ratio from a host; and in response to receiving the first ratio, scheduling a plurality of the first commands and a plurality of the second commands to be executed in the nonvolatile memory such that a second ratio matches with the first ratio, wherein the second ratio is a ratio of a first total period to a second total period, the first total period being a total of the first execution period of each of the plurality of the first commands, and the second total period being a total of the second execution period of each of the plurality of the second commands.
“some storage systems… operate on multiple memory dies via different channels in parallel to enhance the system’s sequential write performance” [0002]. Where the different channels are connected between the non-volatile memory die and the controller [0043].
15. The method according to claim 11, further comprising: determining, based on the first and second execution periods and the first ratio, a first upper limit of the number of the first commands to be queued in a first queue before transmitting the plurality of the first commands to the nonvolatile memory.
9. The method according to claim 8, further comprising: determining, based on the first and second execution periods and the first ratio, a first upper limit of the number of the first commands to be queued in a first queue before transmitting the plurality of the first commands to the nonvolatile memory.
16. The method according to claim 15, wherein the first upper limit is determined such that the second ratio matches with the first ratio.
10. The method according to claim 9, wherein the first upper limit is determined such that the second ratio matches with the first ratio.
17. The method according to claim 11, further comprising: managing a cumulative weight; determining that one of the plurality of the first commands starts to be executed in the nonvolatile memory; in response to determining that the one of the plurality of the first commands starts to be executed in the nonvolatile memory, updating the cumulative weight by executing a first operation that includes one of an addition operation or a subtraction operation to the cumulative weight; determining that one of the plurality of the second commands starts to be executed in the nonvolatile memory; in response to determining that the one of the plurality of the second commands starts to be executed in the nonvolatile memory, updating the cumulative weight by executing a second operation that is the other of the addition operation or the subtraction operation from the first operation to the cumulative weight; and determining, based on whether or not the cumulative weight is larger than a threshold value, which of the first and second commands to be executed next in the nonvolatile memory.
11. The method according to claim 8, further comprising: managing a cumulative weight; determining that one of the plurality of the first commands starts to be executed in the nonvolatile memory; in response to determining that the one of the plurality of the first commands starts to be executed in the nonvolatile memory, updating the cumulative weight by executing a first operation that includes one of an addition operation or a subtraction operation to the cumulative weight; determining that one of the plurality of the second commands starts to be executed in the nonvolatile memory; in response to determining that the one of the plurality of the second commands starts to be executed in the nonvolatile memory, updating the cumulative weight by executing a second operation that is the other of the addition operation or the subtraction operation from the first operation to the cumulative weight; and determining, based on whether or not the cumulative weight is larger than a threshold value, which of the first and second commands to be executed next in the nonvolatile memory.
18. The method according to claim 17, wherein the first operation is the subtraction operation and the second operation is the addition operation, the cumulative weight is updated by subtracting a first value from the cumulative weight or by adding a second value to the cumulative weight, the first value being a value corresponding to the first execution period, the second value being larger than the first value and being a value corresponding to the second execution period, and the method further comprises: determining that the cumulative weight is larger than the threshold value; and in response to determining that the cumulative weight is larger than the threshold value, determining the first command to be executed next in the nonvolatile memory.
12. The method according to claim 11, wherein the first operation is the subtraction operation and the second operation is the addition operation, the cumulative weight is updated by subtracting a first value from the cumulative weight or by adding a second value to the cumulative weight, the first value being a value corresponding to the first execution period, the second value being larger than the first value and being a value corresponding to the second execution period, and the method further comprises: determining that the cumulative weight is larger than the threshold value; and in response to determining that the cumulative weight is larger than the threshold value, determining the first command to be executed next in the nonvolatile memory.
19. The method according to claim 17, further comprising: determining, based on whether or not the cumulative weight is larger than the threshold value, whether to suspend the one of the plurality of the second commands, which is being executed in the nonvolatile memory.
13. The method according to claim 11, further comprising: determining, based on whether or not the cumulative weight is larger than the threshold value, whether to suspend the one of the plurality of the second commands, which is being executed in the nonvolatile memory.
20. The method according to claim 11, wherein the first command is a read command and the second command is a program command or an erase command.
14. The method according to claim 8, wherein the first command is a read command and the second command is a program command or an erase command.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the non-volatile memory from the instant application to be a plurality of memory dies connected to the controller through a plurality of channels as taught by Yang.
One of ordinary skill in the art would have been motivated to make this modification because it allows for increased write speed and enhances the systems sequential write performance as taught by Yang in [0002].
Allowable Subject Matter
Claims 2-4 and 12-14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims. However, the claims would only receive the priority date of the filing date of the instant application, 04 December 2025, and the present application would be treated as a continuation-in-part.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 10,956,346 B1 (Ben-Yehuda) – the system tracks an incoming read/write ratio to determine how to process requests, and sets corresponding read and write limits based on the incoming ratio of commands. However, it does not receive a read/write ratio corresponding to an amount of time the system should devote to each of read and write requests as claimed [Col 18: lines 30-50].
US Patent Application Publication No. US 2019/0079676 A1 (Seo) – teaches to calculate an execution time of each of the various commands execute to non-volatile NAND devices (120) with an execution time calculator (222) [Fig. 2] [0017-0019]. The calculated time may be used to suspend operations for various channels of the memory system [Fig. 4B-4C] [0023-0026]. However, the execution time is only used in the suspend operations and to determine a total execution time of queued commands [Fig. 5] [0005-0006] [0027-0028]. The execution time is not used to determine an execution time ratio between different commands and execute commands according to a ratio received from the host as claimed.
US Patent Application Publication No. US 2020/0363955 A1 (Ji) – teaches using the total program (tPROG) and read (tR) times as well as the ratio of read and write operations to determine a number of die to allocate [Figs. 10-13] [0189-219]. However, the ratio of time spent on read/write operations is not received from a host and is not controlled according to a ratio received from the host as claimed.
US Patent Application Publication No. US 2021/0279196 A1 (Jinn) – teaches to control a scheduling ratio (350) of read and write operations for a period of time (360) [Fig. 3B] [0042-0046]. However, the scheduling ratio is determined based on a number of read and write commands received from the host and based on a write amplification factor (370), and accordingly, is not determined according to a ratio received from the host as claimed, and is not a ratio of the execution times of the read and write commands as claimed, but rather a ratio of a number of the commands.
Jiacheng Zhang et. al., “ParaFS: A Log-Structured File System to Exploit the Internal Parallelism of Flash Devices”, 24 June 2016, Proceedings of the 2016 USENIX Annual Technical Conference (USENIC ATC ’16), pgs. 87-100 (Zhang) – teaches a parallelism-aware flash scheduler that accounts for the substantially different execution times of read and write operations based on assigned weights, where the assigned weights may be based on measured latencies in the respective read and write commands. It then assigns writes to the least busy channel as determined with those weights and the number of respective commands queue for each die/channel. It allocates equal time slices to write/erase requests and read requests [§3.4 Parallelism-Aware-Scheduling, ¶¶1-5, pgs. 92-93]. However, it does not teach receiving a ratio of execution times for read/write requests from the host, controlling the memory such that the received ratio is achieved, or suspending a request based on a ratio of executed times for read/write requests.
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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