DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 14, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings have been considered and accepted by the examiner.
Specification
The title, abstract, and specification have been considered and accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 8, 14, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PGPub 2024/0095181 to Lee.
Regarding claim 1, Lee discloses a storage device, comprising:
a non-volatile memory device configured to store a first set of a map loading unit to convert a logical address into a physical address (see paragraphs 36 and 40, map data may be stored in the NAND flash memory device 100); and
a storage controller configured to store a second set of map loading unit in a volatile memory based on the first set of the map loading unit (see paragraphs 49, 76 and 77, the host controller may request map segments and store it in host memory 410),
wherein the storage controller is further configured to:
based on a first command received from a host device, load a first map loading unit corresponding to the first command of the first set of map loading unit from the non-volatile memory device (see paragraphs 49 and 81, the host controller may send a request for map data to be loaded into the cache);
store the first map loading unit in the volatile memory (see paragraphs 49 and 81, the requested map data is stored in the cache in the storage controller);
obtain a first logical address associated with a second command queued to a command queue of the host device (see paragraphs 100-102, a logical address in a queued command is checked);
load a second map loading unit of the first set of the map loading unit, corresponding to the obtained first logical address, from the non-volatile memory (see paragraph 102, a map segment for the identified logical address is request from the storage device to be cached); and
store the second map loading unit the volatile memory (see paragraphs 49 and 81, the request map data is stored in the cache of the storage controller).
Regarding claim 19, Lee discloses a storage system, comprising a host device comprising a host memory comprising a command queue (see paragraph 100); and
the system of claim 1.
Regarding claim 2, Lee discloses the storage device, wherein the storage controller is further configured to, after loading the second map loading unit to the volatile memory:
fetch the second command from the host device (see paragraph 48, the host controller may store the command temporarily and then send the request to the storage device);
obtain the first logical address from the fetched second command (see paragraph 49, the command and the address corresponding thereto are provided to the storage device);
determine a physical address of the non-volatile memory device corresponding to the first logical address, based on the second loading unit stored in the volatile memory (see paragraph 49, the logical address may be translated based on the map stored in the host memory); and
transmit a memory device command instructing the non-volatile memory device to perform an operation associated with the second command, and the physical address, to the non-volatile memory device (see paragraph 49).
Regarding claim 3, Lee discloses the storage device, wherein the second command is a command to be processed by the storage controller following the first command being fetched from the host device (see paragraph 100, commands being queued mean there is a sequence of subsequent commands that are stored in the queue).
Regarding claim 4, Lee discloses the storage device, wherein the storage controller is further configured to:
obtain a second logical address associated with a third command queued to the command queue (see paragraph 100, multiple commands are queued in the host memory);
load, from the non-volatile memory device, a third map loading unit corresponding to the obtained second logical address of the first set of the map loading unit (see paragraph 102); and
store the third map loading unit in the volatile memory device (the requested mapping information is stored in the host memory), and
wherein the third command is a command to be processed by the storage controller following a second command (the nature of a command queue is that commands are processed in sequential order).
Regarding claim 7, Lee discloses the storage device,
wherein the first set of the map loading unit comprises the second set of the map loading unit (the first set is all the map data segments and the second set is a request segment of map data which would necessarily be a subset of all the map data); and
wherein a size of het second set of the map loading unit is smaller than a size of the first set of the map loading unit (a subset of all the map data would be a smaller set than all the map data).
Regarding claim 8, Lee discloses the storage device, wherein the first set of the map loading unit comprises a plurality of logical addresses corresponding to a total number of logic blocks and a plurality of physical addresses corresponding to the plurality of logical addresses (see paragraph 40, the map data is the translation of logical addresses to all the physical addresses that are addressable).
Regarding claim 14, Lee discloses the storage device, wherein the first command is a read command, a write command, or a TRIM command (see paragraph 76, when the command is a read command the host controller may request map segments).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US PGPub 2022/0114087 to Kim et al. (“Kim”).
As applied in the rejection above, Lee discloses a storage device with a storage controller for loading map loading units.
Regarding claim 5, Lee does not disclose the storage controller is further configured to store the second map loading unit in the volatile memory and then the store the third map loading unit in a sequence following the second map loading unit in the volatile memory. Kim discloses a memory system that caches map data entries sequentially in a volatile memory (see fig. 6 and paragraph 96 of Kim). It would have been obvious at the time the application was filed to a person of ordinary skill in the art for the system of Lee to store the map loading units in the volatile memory in a sequence in order to keep the map data units together in the volatile memory without wasting memory space.
Regarding claim 9, Lee does not disclose the storage controller is further configured to, overwrite victim data that is a part of the second set of the map loading unit, with the second map loading unit to store the second map loading unit in the volatile memory. Kim discloses a memory system that caches map data that removes the LRU map chunk to make room for a newly loaded map chunk when there is no residual space (see paragraph 113 of Kim). It would have been obvious at the time the application was filed to a person of ordinary skill in the art to overwrite victim data in the volatile memory with newly loading map data when the volatile memory has run out of space for storing new map data entries.
Allowable Subject Matter
Claims 15-18 are allowed.
Claims 6, 10-13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not disclose or suggest receiving a first command from a host device and obtaining a first logical address associated with a second command queued to a command queue of the host device, and a second logical address associated with a third command queued to a command queue and loading map loading units corresponding to the first command, first logical address, and second logical address.
The prior art does not disclose or suggest obtaining, from the host device, a number of logic blocks associated with the second command queued to a command queue and loading at least one map loading unit corresponding to the first logical address and the number of logic blocks.
The prior art does not disclose or suggest obtaining a plurality of logical addresses associated with a plurality of commands queued to the command queue and determining the victim data to overwrite based on the plurality of logical addresses.
The prior art does not disclose or suggest obtaining an address of the host memory in which a logical address associated with the second command is stored.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPub 2019/0317894 discloses address map caching for a memory system but does not disclose the claimed features.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D TSUI whose telephone number is (571)270-3253. The examiner can normally be reached Monday-Friday 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL D TSUI/ Primary Examiner, Art Unit 2132
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