Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application filed August 14, 2025. Claims 1-20 are presented for examination. Claim 1 is an independent claim.
Priority
Examiner acknowledges the claims for domestic priority under 35 U.S. C. 119 (e) to continuation application PCT/CN2023/079105 which was filed March 1, 2023.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted August 14, 2025.
Drawings
The drawings filed August 14, 2025 are accepted by the examiner.
Abstract
The abstract filed August 14, 2025 is accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428,46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046,29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CPR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of application No. 18703194 Patent 12444365 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims recite a display substrate, comprising: a base substrate; a plurality of sub-pixels on the base substrate, wherein the plurality of sub-pixels are arranged in a first direction and a second direction, and at least one of the plurality of sub-pixels comprises a light emitting element; a plurality of pixel driving circuits on the base substrate, wherein the plurality of pixel driving circuits are arranged in the first direction and the second direction and are configured to drive the light emitting elements of the plurality of sub-pixels respectively, and at least one of the plurality of pixel driving circuits comprises at least two transistors; a plurality of data lines on the base substrate, wherein the plurality of data lines respectively extend in the second direction; and a plurality of control signal lines on the base substrate, each of the plurality of control signal lines comprising a portion extending in the first direction and being configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on, wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region, therefore the same limitations as claimed in application No. 18703194 Patent 12444365 B2.
This is an obviousness-type double patenting rejection.
Application 19300642
Application 18703194 Patent 12444365 B2
A display substrate, comprising: a base substrate; a plurality of sub-pixels on the base substrate, wherein the plurality of sub-pixels are arranged in a first direction and a second direction, and at least one of the plurality of sub-pixels comprises a light emitting element; a plurality of pixel driving circuits on the base substrate, wherein the plurality of pixel driving circuits are arranged in the first direction and the second direction and are configured to drive the light emitting elements of the plurality of sub-pixels respectively, and at least one of the plurality of pixel driving circuits comprises at least two transistors; a plurality of data lines on the base substrate, wherein the plurality of data lines respectively extend in the second direction; and a plurality of control signal lines on the base substrate, each of the plurality of control signal lines comprising a portion extending in the first direction and being configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on, wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region.
14. The display substrate according to claim 1, further comprising an initialization voltage signal line on the base substrate, wherein the initialization voltage signal line comprises a portion extending in the first direction and is configured to provide an initialization voltage signal to the at least one pixel driving circuit; wherein in a frame of driving the pixel driving circuits of a row of sub-pixels, the control signal on the control signal line controls the at least two transistors of the at least one pixel driving circuit to turn on in at least one first time period, and the initialization voltage signal on the initialization voltage signal line is provided to the at least one pixel driving circuit in a second time period, and the first time period is separated from the second time period in timing; and wherein the initialization voltage signal line and the control signal line are located in different conductive layers, an orthographic projection of the initialization voltage signal line on the base substrate overlaps at least partially with an orthographic projection of the control signal line on the base substrate to form an overlapping portion, and in at least one of the sub-pixels, a ratio of an area of the overlapping portion to an area of the orthographic projection of the control signal line on the base substrate is in a range from 60% to 100%.
A display substrate, comprising: a base substrate; a plurality of sub-pixels provided on the base substrate, wherein the plurality of sub-pixels are arranged in a first direction and a second direction, and comprise a light emitting element; a plurality of pixel driving circuits provided on the base substrate, wherein the plurality of pixel driving circuits are arranged in the first direction and the second direction, the plurality of pixel driving circuits are configured to drive the light emitting elements of the plurality of sub-pixels respectively, and at least one pixel driving circuit comprises at least two transistors; an initialization voltage signal line provided on the base substrate, wherein the initialization voltage signal line comprises a portion extending in the first direction, and the initialization voltage signal line is configured to provide an initialization voltage signal to the at least one pixel driving circuit; and a control signal line provided on the base substrate, wherein the control signal line comprises a portion extending in the first direction, and the control signal line is configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on, wherein in a frame of driving the pixel driving circuits of a row of sub-pixels, the control signal on the control signal line controls the at least two transistors of the at least one pixel driving circuit to turn on in at least one first time period, and the initialization voltage signal on the initialization voltage signal line is provided to the at least one pixel driving circuit in a second time period, wherein the first time period is separated from the second time period in timing; and the initialization voltage signal line and the control signal line are located in different conductive layers, an orthographic projection of the initialization voltage signal line on the base substrate overlaps at least partially with an orthographic projection of the control signal line on the base substrate, and in at least one of the sub-pixels, a ratio of an area of an overlapping portion to an area of the orthographic projection of the control signal line on the base substrate is in a range from 60% to 100%.
Allowable Subject Matter
Claims 1-20 are allowable upon overcoming the double-patenting rejections above. The following is an examiner’s statement of reasons for indicating allowable subject matter: The prior art is silent regarding “a display substrate, comprising: a base substrate; a plurality of sub-pixels on the base substrate, wherein the plurality of sub-pixels are arranged in a first direction and a second direction, and at least one of the plurality of sub-pixels comprises a light emitting element; a plurality of pixel driving circuits on the base substrate, wherein the plurality of pixel driving circuits are arranged in the first direction and the second direction and are configured to drive the light emitting elements of the plurality of sub-pixels respectively, and at least one of the plurality of pixel driving circuits comprises at least two transistors; a plurality of data lines on the base substrate, wherein the plurality of data lines respectively extend in the second direction; and a plurality of control signal lines on the base substrate, each of the plurality of control signal lines comprising a portion extending in the first direction and being configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on, wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region”, as recited in claim 1.
The closest prior arts are Mou et al. (US 20220044636 Al), Dong et al. (US 20210376046 Al) and Yokoyama et al. (US 20210027718 A1).
Mou et al. (US 20220044636 Al) discloses a display substrate (Mou, see Abstract, where Mou discloses that a display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate, a sub-pixel includes an organic light emitting element and a pixel circuit, the organic light emitting element includes a first electrode, a light emitting layer and a second electrode which are stacked, the second electrode is electrically connected to the pixel circuit. The display substrate further includes an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer, and a third conductive layer, the source-drain metal layer includes a first power signal line, and the third conductive layer includes a second power signal line; the display substrate further includes reset power signal lines, the reset power signal lines include a first reset power signal line and a second reset power signal line which are electrically connected to the pixel circuit), comprising: a base substrate (Mou, see Base substrate 100 in figure 6 and paragraph [0050], where Mou discloses an array substrate, which includes a base substrate 100); a plurality of sub-pixels on the base substrate (Mou, see subpixels 110 through 130 on base substrate 100 in figure 7 and paragraph [0134], where Mou discloses FIG. 6-FIG. 7, a display substrate 1000 provided by the embodiments of the present disclosure includes a base substrate 100 and a plurality of repeating units 11 arranged along a first direction (that is, Y direction) and a second direction (that is, X) on the base substrate 100, the first direction intersects the second direction. For example, the first direction is perpendicular to the second direction. Each repeating unit 11 includes a plurality of sub-pixels 22, for example, including a first color subpixel 110 and a second color sub-pixel 120. Sub-pixel 22 of each color includes an organic light emitting element 220 and a pixel circuit 221), wherein the plurality of sub-pixels are arranged in a first direction and a second direction (Mou, see 110 through 130 in figure 7), and at least one of the plurality of sub-pixels comprises a light emitting element (Mou, see paragraph [0134], where Mou discloses that sub-pixel 22 of each color includes an organic light emitting element 220 and a pixel circuit 221. The pixel circuit 221 is used to drive the organic light emitting element 220 to emit light); a plurality (Mou, see plurality of repeating units 11 in figure 7 and as per figure 6 Mou discloses that multiple repeating units 11 contain multiple driving circuits 222) of pixel driving circuits (Mou, see driving circuits 222 on base substrate 100 in figure 6) on the base substrate (Mou, see driving circuits 222 on base substrate 100 in figure 6), wherein the plurality of pixel driving circuits (Mou, see plurality of repeating units 11 in figure 7 and as per figure 6 Mou discloses that multiple repeating units 11 contain multiple driving circuits 222) are arranged in the first direction and the second direction (Mou, see plurality of repeating units 11 in multiple directions in figure 7 and as per figure 6 Mou discloses that multiple repeating units 11 contain multiple driving circuits 222 and therefore teaching or suggesting plurality of driving circuits 222 in multiple directions) and are configured to drive the light emitting elements of the plurality of sub-pixels respectively (Mou, see paragraph [0134], where Mou discloses that the pixel circuit 221 is used to drive the organic light emitting element 220 to emit light. The pixel circuit 221 includes a driving circuit 222. The driving circuit 222 of the first color sub-pixel 110 includes a first driving transistor 111, the driving circuit 222 of the second color sub-pixel 120 includes a second driving transistor 121, and a channel width-length ratio of the first driving transistor 111 is greater than a channel width-length ratio of the second driving transistor 121), and at least one of the plurality of pixel driving circuits comprises at least two transistors (Mou, see paragraph [0134], where Mou discloses that the pixel circuit 221 is used to drive the organic light emitting element 220 to emit light. The pixel circuit 221 includes a driving circuit 222. The driving circuit 222 of the first color sub-pixel 110 includes a first driving transistor 111, the driving circuit 222 of the second color sub-pixel 120 includes a second driving transistor 121, and a channel width-length ratio of the first driving transistor 111 is greater than a channel width-length ratio of the second driving transistor 121); a plurality of data lines on the base substrate (Mou, see plurality of repeating units 11 in multiple directions in figure 7 and as per figure 6 Mou discloses that multiple repeating units 11 contain multiple driving circuits 222, therefore teaching or suggesting plurality of driving circuits 222 in multiple directions and multiple driving circuits 222 having multiple data lines Vd as per figures 8, 7 and 6 and paragraph [0147], where Mou discloses as per FIG. 8, a first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor Tl, a second electrode of the data writing transistor T2 is configured to be electrically connected to a data line V d to receive the data signal), wherein the plurality of data lines respectively extend in the second direction (Mou, see 11 in figure 7 and figure 6 where multiple sub-pixel 120 have multiple pixel circuit 221 and therefore multiple data lines Vd in multiple directions); and a plurality of control signal lines on the base substrate (Mou, see first reset control signal Rst1, second reset control signal Rst2, first light emitting reset control signal EM1, second light emitting reset control signal EM2 in figure 8), each of the plurality of control signal lines comprising a portion extending in the first direction and being configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on (Mou, see paragraph [0147], where Mou discloses and a gate electrode of the first reset transistor T6 is configured to be electrically connected to a first reset control signal line Rst1 to receive a first sub-reset control signal; a first electrode of the second reset transistor T7 is configured to be electrically connected to a second reset power supply terminal Vinit2 to receive a second reset signal, a second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organic light emitting element 220, and a gate electrode of the second reset transistor T7 is configured to be electrically connected to a second reset control signal line Rst2 to receive a second sub-reset control signal; a first electrode of the first light emitting control transistor T4 is electrically connected to the first voltage terminal VDD, a second electrode of the first light emitting control transistor T4 is electrically connected to the first electrode of the driving transistor Tl, and a gate electrode of the first light emitting control transistor T4 is configured to be electrically connected to a first light emitting control signal line EM1 to receive a first light emitting control signal; a first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor Tl, a second electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the organic light emitting element 220, and a gate electrode of the second light emitting control transistor T5 is configured to be electrically connected to a second light emitting control signal line EM2 to receive a second light emitting control signal; and the first electrode of the organic light emitting element 220 is electrically connected to a second voltage terminal VSS).
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Mou does not explicitly disclose wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region.
Dong et al. (US 20210376046 Al) discloses wherein the plurality of data lines comprises a first data line and a second data line, the plurality of control signal lines comprises a first control signal line and a second control signal line.
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Dong does not explicitly disclose wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region.
Yokoyama et al. (US 20210027718 A1).discloses a data lines (Yokoyama, see first data line Da and second data line Db in figure 10 (b) comprises a first data line and a second data line adjacent to the first data line (Yokoyama, see first data line Da and second data line Db in figure 10 (b), the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal (Yokoyama, see first control signal Ea and second control signal Eb in figure 10(a)), and an enclosure forming at least one hollow region (Yokoyama, see figure 11).
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Yokoyama does not explicitly disclose wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region.
Thus the prior arts of Mou et al. (US 20220044636 Al), Dong et al. (US 20210376046 Al) and Yokoyama et al. (US 20210027718 A1) are silent regarding “a display substrate, comprising: a base substrate; a plurality of sub-pixels on the base substrate, wherein the plurality of sub-pixels are arranged in a first direction and a second direction, and at least one of the plurality of sub-pixels comprises a light emitting element; a plurality of pixel driving circuits on the base substrate, wherein the plurality of pixel driving circuits are arranged in the first direction and the second direction and are configured to drive the light emitting elements of the plurality of sub-pixels respectively, and at least one of the plurality of pixel driving circuits comprises at least two transistors; a plurality of data lines on the base substrate, wherein the plurality of data lines respectively extend in the second direction; and a plurality of control signal lines on the base substrate, each of the plurality of control signal lines comprising a portion extending in the first direction and being configured to provide a control signal to the at least one pixel driving circuit so as to control the at least two transistors of the at least one pixel driving circuit to turn on, wherein the plurality of data lines comprises a first data line and a second data line adjacent to the first data line, the plurality of control signal lines comprises a first control signal line and a second control signal line adjacent to the first control signal, and each of the first control signal line and the second control signal line intersects with each of the first data line and the second data line so as to enclose and form at least one hollow region”, as recited in claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Lee (US 11429238 B2) discloses a base substrate through which a hole is defined, a cover portion, a first sensing electrode, a second sensing electrode, a dummy electrode, and a ground line. The cover portion surrounds the hole and includes at least one cover pattern. The first sensing electrode includes first sensing patterns. The second sensing electrode includes second sensing patterns. The dummy electrode includes dummy patterns disposed between the first sensing patterns and the second sensing patterns. The ground line is electrically connected to the cover portion through at least some of the dummy patterns.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/Primary Examiner, Art Unit 2624
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