DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 17 of U.S. Patent No. 12,407,346.
Although the claims at issue are not identical, they are not patentably distinct from each other because they merely omit features that is recited in the claim 1 of US Patent such as “a buffer circuit connected between the third terminal and the capacitive element.”. The omission of the features results in the claim that are broader in the scope than the claims of the Patent claims.
Furthermore, the instant application claims 1 and 9 recite a switch having an input terminal, an output terminal and a control terminal which correspond respectively to a first terminal, a second terminal and a third terminal of US Patent claims 1 and 17. Both the instant application and the US patent disclose a capacitor coupling the control terminal to the first node, and both further disclose a discharge circuit coupling the first node to the input terminal.
Given that the instant application already teaches the control terminal being capacitively coupled to the first node, and the first node being conductively coupled to the input terminal through a discharge circuit, arranging the discharge circuit between the input terminal and the control terminal is an obvious and predictable variation in circuit placement. A person of ordinary skill in the art would have recognized that, because the control terminal and input terminal are already indirectly connected through the first node would have been a routine design choice yielding the same functional discharge path.
Accordingly, the differences between the instant application claim 1 and the US Patent claim 1 do not render the instant application claim patentably distinct, particularly where the remaining elements of the claimed inventions are otherwise identical or substantially similar (see table below).
Claims 2-8 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-7 and 18 of U.S. Patent No. 12,184,272.
Instant Application No. 19/300,829
U.S. Patent No. 12,407,346
1. A switch comprising: a first MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the source coupled to the channel-forming region and coupled with an input terminal of the switch, the drain coupled with an output terminal of the switch, and the gate coupled to a first node of the switch; a diode coupling the input terminal with the first node; a capacitor coupling a control terminal of the switch with the first node, the control terminal being configured to receive a control signal for the switch; and a discharge circuit coupling the first node with the input terminal, the discharge circuit arranged between the input terminal and the control terminal of the first MOS transistor and configured to conduct only when a voltage between the first node and the input terminal is greater than or equal to a threshold.
3. The switch of claim 1, further comprising a buffer circuit coupled between the control terminal and the capacitor.
1. A switch comprising: a first MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the source connected to the channel-forming region and coupled with a first terminal of the switch, the drain coupled with a second terminal of the switch, and the gate connected to a first node of the switch; a diode coupling the first terminal with the first node; a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch; a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold; and a buffer circuit connected between the third terminal and the capacitive element.
2. The switch of claim 1, wherein the discharge circuit comprises two Zener diodes series connected and reversely connected with respect to each other between the first node and the input terminal.
2. The switch according to claim 1, wherein the discharge circuit comprises two Zener diodes series connected and reversely connected with respect to each other between the first node and the first terminal.
4. The switch of claim 3, wherein the buffer circuit is configured to deliver a binary signal having a first level corresponding to a power supply voltage and a second level corresponding to a zero voltage.
3. The switch according to claim 1, wherein the buffer circuit is configured to deliver a binary signal having a first level corresponding to a power supply voltage and a second level corresponding to a zero voltage.
5. The switch of claim 1, wherein an anode of the diode is oriented towards the input terminal.
4. The switch according to claim 1, wherein the diode has its anode towards the first terminal.
6. The switch of claim i, further comprising a resistor in series with the first MOS transistor, wherein the resistor is located between the input terminal and the output terminal.
5. The switch according to claim 1, further comprising a resistor in series with the first MOS transistor, wherein the resistor is located between the first and second terminals.
7. The switch of claim 6, wherein the resistor is coupled between the input terminal and the source of the first MOS transistor.
6. The switch according to claim 5, wherein the resistor is connected between the first terminal and the source of the first MOS transistor.
8. The switch of claim 1, further comprising a second MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the gate of the second MOS transistor being coupled to the gate of the first MOS transistor, the source of the second MOS transistor being coupled to the source of the first MOS transistor and to the channel-forming region of the second MOS transistor, and the drain of the second MOS transistor being coupled to the input terminal.
7. The switch according to claim 1, further comprising a second MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the gate of the second MOS transistor connected to the gate of the first MOS transistor, the source of the second MOS transistor connected to the source of the first MOS transistor and with a channel-forming region of the second MOS transistor, and the drain of the second MOS transistor connected to the first terminal.
9. An analog-to-digital converter comprising: a plurality of switches comprising a first switch, a second switch, a third switch and a fourth switch, each switch of the plurality of switches comprising: a first MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the source coupled to the channel-forming region and coupled with an input terminal of the switch, the drain coupled with an output terminal of the switch, and the gate coupled to a first node of the switch; a second MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the gate of the second MOS transistor coupled to the gate of the first MOS transistor, the source of the second MOS transistor coupled to the source of the first MOS transistor and to the channel-forming region of the second MOS transistor, and the drain of the second MOS transistor coupled to the input terminal; a diode coupling the input terminal with the first node; a capacitor coupling a control terminal of the switch with the first node, the control terminal being configured to receive a control signal for the switch; and a discharge circuit coupling the first node with the input terminal, the discharge circuit arranged between the input terminal and the control terminal of the first MOS transistor and configured to conduct only when a voltage between the first node and the input terminal is greater than or equal to a threshold, wherein the first and second switches have input terminals coupled with a first input of the converter, wherein the third and fourth switches have input terminals coupled with a second input of the converter, wherein the first and third switches have output terminals coupled with a first output, wherein the second and fourth switches have output terminals coupled with a second output, wherein control terminals of the first and fourth switches are configured to receive a first control signal, and wherein control terminals of the second and third switches are configured to receive a second control signal.
17. An analog-to-digital converter comprising: a plurality of switches comprising a first switch, a second switch, a third switch and a fourth switch, each switch of the plurality of switches comprising: a first MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the source connected to the channel-forming region and coupled with a first terminal of the switch, the drain coupled with a second terminal of the switch, and the gate connected to a first node of the switch; a second MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the gate connected to the gate of the first MOS transistor, the source of the second MOS transistor connected to the source of the first MOS transistor and with a channel-forming region of the second MOS transistor, and the drain of the second MOS transistor connected to the first terminal; a diode coupling the first terminal with the first node; a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch; and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold, wherein the first and second switches have their first terminals coupled with a first input of the converter, wherein the third and fourth switches have their first terminals coupled with a second input of the converter, wherein the first and third switches have their second terminals coupled with a first output of a sampling circuit of the converter, wherein the second and fourth switches have their second terminals coupled with a second output of a sampling circuit of the converter, wherein third terminals of the first and fourth switches are configured to receive a first control signal, and wherein the third terminals of the second and third switches are configured to receive a second control signal.
10. The converter of claim 9, wherein each switch further comprises a buffer circuit coupled between the control terminal and the capacitor, and wherein each discharge circuit comprises two Zener diodes series connected and reversely connected with respect to each other between the first node and the input terminal.
18. The converter according to claim 17, wherein each switch further comprises a buffer circuit connected between the third terminal and the capacitive element, and wherein each of the discharge circuit comprises two Zener diodes series connected and reversely connected with respect to each other between the first node and the first terminal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huijsing et al. (US 2016/0013787) in view of Souma (US 8111491).
Regarding claim 1, Huijsing discloses a switch [fig. 1] comprising: a first MOS transistor [MN1] comprising a source [source MN1], a drain [drain MN1], a gate [gate MN1], and a channel-forming region, the source coupled to the channel-forming region and coupled with an input terminal [Vinp terminal] of the switch, the drain coupled with an output terminal [Voutp terminal] of the switch, and the gate coupled to a first node [node between MN1 and C11] of the switch; a diode [Dr11] coupling the input terminal with the first node; a capacitor [C11] coupling a control terminal [node CLKp] of the switch with the first node, the control terminal being configured to receive a control signal [signal Clkp] for the switch. Huijsing does not explicitly disclose a discharge circuit coupling the first node with the input terminal, the discharge circuit arranged between the input terminal and the control terminal of the first MOS transistor and configured to conduct only when a voltage between the first node and the input terminal is greater than or equal to a threshold.
However, Souma discloses [fig. 2] a discharge circuit [510] coupling a first node [node between 501 and 510] with the input terminal [501], the discharge circuit arranged between an input terminal [501] and the control terminal [gate 508] of first MOS transistor [508] and the configured to conduct only [discharge electric charges] when a voltage between the first node and the input terminal [gate source voltage] is greater than or equal to a threshold [cl. 1-cl. 2]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Huijsing by incorporating the discharge circuit as taught in Souma in order to prevent overvoltage failure of the gate.
Regarding claim 2, Huijsing in view of Souma discloses [see fig. 2] wherein the discharge circuit comprises two Zener diodes series [511 and 512] connected and reversely connected with respect to each other between the first node and the first terminal.
Regarding claim 5, Huijsing in view of Souma discloses [see fig. 2] wherein an anode of the diode [A1] is oriented towards the input terminal.
Regarding claim 19, Huijsing discloses a method of switching comprising: providing a switch [fig. 1] having an input terminal [Vinp terminal], an output terminal [Voutp terminal], and a control terminal [node CLKp]; applying an input voltage [Vinp] to the input terminal; applying a control signal [CLKp] to the control terminal to control a conductive state of the switch [on state]; capacitively coupling the control signal to a gate of a first MOS transistor [MN1] through a capacitor [C11], the first MOS transistor comprising a source [source MN1] coupled to a channel-forming region of the first MOS transistor and coupled to the input terminal, and a drain coupled to the output terminal; coupling the input terminal to the gate through a diode [Dr11] to establish a gate voltage based on the input voltage. Huijsing does not discloses monitoring a voltage difference between the gate and the input terminal using a discharge circuit arranged between the input terminal and the control terminal of the first MOS transistor; and conducting current through the discharge circuit only when the voltage difference between the gate and the input terminal is greater than or equal to a threshold, to protect the first MOS transistor from overvoltage conditions.
However, Souma discloses [fig. 2] monitoring a voltage difference between the gate [gate 508] and the input terminal [501] using a discharge circuit [510] arranged between the input terminal and the control terminal of first MOS transistor [508]; and conducting current through the discharge circuit only when the voltage difference between the gate and the input terminal is greater than or equal to a threshold, to protect the first MOS transistor from overvoltage conditions [cl. 1-cl. 2]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Huijsing by incorporating the discharge circuit as taught in Souma in order to prevent overvoltage failure of the gate.
Regarding claim 20, Huijsing in view of Souma discloses wherein the discharge circuit comprises two Zener diodes series [511/512] connected and reversely connected with respect to each other between the gate and the input terminal, and wherein conducting current through the discharge circuit occurs when the voltage difference exceeds an avalanche voltage of a first Zener diode [511] plus a threshold voltage of a second Zener diode [512].
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huijsing et al. in
view of Souma further in view of Biskup (US 2014/0266381A1)
Regarding claim 6, Huijsing in view of Souma discloses all the features with respect to claim 1 as indicated above. Huijsing in view of Souma discloses does not explicitly disclose a resistor in series with the first MOS transistor, wherein the resistor is located between the input terminal and the output terminal.
However, Biskup discloses [see fig. 2] wherein a resistor [R1] in series with a first
transistor [S1a], wherein the resistor is located between [terminal to Cell_V+] input and output
terminals [terminal between Sla and S2a]. It would have been obvious to one of ordinary skill in
the art before the effective filling date of the claimed invention to modify the invention of
Huijsing in view of Souma by incorporating a resistor as taught in Biskup in order to limit the current to transistor.
Regarding claim 7, Huijsing in view of Souma further in view of Biskup discloses [see fig. 2] wherein the resistor is connected between the input terminal and the source of the first MOS transistor.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huijsing et al. in
view of Souma further in view of Allali et al. (WO 2020229490 A1 and Allali hereinafter)
Regarding claim 8, Huijsing in view of Souma discloses all the features with respect to claim 1 as indicated above. Huijsing in view of Souma discloses docs not explicitly disclose a second MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the gate of the second MOS transistor being coupled to the gate of the first MOS transistor, the source of the second MOS transistor being coupled to the source of the first MOS transistor and to the channel-forming region of the second MOS transistor, and the drain of the second MOS transistor being coupled to the input terminal.
However, Allali discloses [fig. 3] a second transistor MOS [Q2] a source, a drain, a gate, and a channel-forming region, the having the gate of the first MOS transistor, the source of the second MOS transistor being coupled to the source of first MOS transistor [Q1] and to the channel-forming region of the second MOS transistor, and the drain of the second MOS transistor being coupled to the input terminal. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Huijsing in view of Souma by incorporating a resistor as taught in Allali in order to control the circuit.
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and would be allowable upon timely filing of a terminal disclaimer.
Claims 11-18 would be allowable upon timely filing of a terminal disclaimer
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, Huijsing in view of Souma does not explicitly disclose a buffer circuit coupled between the control terminal and the capacitor.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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