DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 15 August 2025.
Claims 1-20 are pending and have been presented for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9, 18 and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by NICOL (WO 2019/040339).
1. NICOL discloses A processor, comprising: a plurality of execution units (see [0028]: multiple processing elements); a plurality of memory units (see [0030]: storage elements); and a compiler (see [0053]-[0054]: software stack includes a compiler; [0055]: software development kit to generate code for the data flow processor) configured to synchronize (see [0032]: first and second set of clusters are synchronized) timing of data flow (see [0038]-[0039]: data is sent to the first cluster and from the first cluster) and instruction flow (see [0032]: circular buffers are loaded with instructions to be executed on the cluster) among the plurality of execution units and the plurality of memory units according to a predetermined temporal relationship (see [0038]-[0039]: data needs for a kernel include a time at which the data is required for processing; [0034]: awaiting arrival of data and begin processing when valid data is available).
2. The processor of claim 1, further comprising an instruction control unit (ICU) configured to issue an instruction to the plurality of execution units (see [0030]: the circular buffers contain the instructions that are executed by the processing elements, these circular buffers are the instruction control units).
3. The processor of claim 2, wherein the plurality of execution units are configured to receive operand data via at least one communication lane and execute the instruction on the operand data (see [0036]-[0037]: data is sent through the second cluster to the first cluster for processing; [0034]: when valid data arrives the processing elements can begin operations).
4. The processor of claim 3, wherein the plurality of memory units is configured to provide the operand data via the at least one communication lane (see [0033]: switching elements are used to transfer data, these switching elements would be the communication lane; [0032]: STE’s store data, this would be the memory units that provide the operand data).
5. The processor of claim 3, wherein the operand data is transmitted between the plurality of execution units without any accompanying metadata (see [0043]: the data operated on by the execution units are input data such as binary data, alphanumeric data, graphical data, etc. the reference does not indicate any metadata that is sent with the data).
6. The processor of claim 3, wherein the plurality of execution units are arranged such that the operand data flows in a first direction across the plurality of execution units (see [0036]-[0037]: data is sent through the second cluster to the first cluster for processing, this would be a first direction; [0059]: data can travel in one direction, such as east).
7. The processor of claim 6, wherein result data of the plurality of execution units flows in a second direction that is opposite the first direction (see [0059]: east-west communication, where data is input from the east, and the generated output is sent west).
9. The processor of claim 1, wherein the plurality of execution units are dedicated to a specific function such that the plurality of execution units are configured to perform a same operation on received data (see [0030]: the processing elements are controlled by a static scheduled circular buffer, static scheduling executes the same code repeatedly, therefore the execution units will be perming the same operation until new code is loaded into the circular buffer).
18. The processor of claim 1, wherein the plurality of execution units comprise at least one of a vector execution module (VXM), a matrix execution module (MXM), a numerical interpretation module (NIM), or a switching and permutation module (SXM) (see [0038]: the processing elements process vectors and tensors, therefore, during processing of these data types the execution unit would be a vector execution module or a matrix execution module).
19. NICOL discloses One or more non-transitory, computer-readable media (see [00124]: computer readable media; [00125]: computer program instructions) storing a compiler (see [0053]-[0054]: software stack includes a compiler; [0055]: software development kit to generate code for the data flow processor) configured to synchronize (see [0032]: first and second set of clusters are synchronized) timing of data flow (see [0038]-[0039]: data is sent to the first cluster and from the first cluster) and instruction flow (see [0032]: circular buffers are loaded with instructions to be executed on the cluster) among a plurality of execution units and a plurality of memory units according to a predetermined temporal relationship (see [0038]-[0039]: data needs for a kernel include a time at which the data is required for processing; [0034]: awaiting arrival of data and begin processing when valid data is available).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over NICOL (WO 2019/040339) in view of ANAND (U.S. Patent #9,281,045).
15. The processor of claim 1 (see NICOL above), wherein the plurality of memory units are organized into a first hemisphere and a second hemisphere, and wherein the plurality of memory units are mirrored between the first hemisphere and the second hemisphere (see ANAND below).
ANAND discloses the following limitations that are not disclosed by NICOL: wherein the plurality of memory units are organized into a first hemisphere and a second hemisphere, and wherein the plurality of memory units are mirrored between the first hemisphere and the second hemisphere (see column 4, lines 16-25: bank A and mirror bank A mirrored across a spine of array read/write circuits). ANAND discloses a DRAM with mirrored banks across a spine of read/write circuits. The memory banks on either side of the spine would be considered the two hemispheres, resulting in memory units that are mirrored between the two hemispheres. This mirrored arrangement minimizes routes and distances between transfer registers (see column 4, lines 23-25).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify NICOL to organize the memory units into hemispheres, as disclosed by ANAND. One of ordinary skill in the art would have been motivated to make such a modification to minimize routes and distances between transfer registers, as taught by ANAND. NICOL and ANAND are analogous/in the same field of endeavor as both references are directed to managing memory units.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over NICOL (WO 2019/040339) in view of GUENTHER (U.S. Patent Application Publication #2007/0162270).
16. The processor of claim 1 (see NICOL above), wherein the plurality of memory units comprise static random access memory (SRAM) (see GUENTHER below).
GUENTHER discloses the following limitations that are not disclosed by NICOL: wherein the plurality of memory units comprise static random access memory (SRAM) (see [0024]: use of DRAM or SRAM for data and instruction memories). The use of DRAM and SRAM for storing data to be used by a processor is well-know and common in the art. There are a limited number of memory types that can be used for storing data. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify NICOL to use SRAM memory units, as disclosed by GUENTHER. One of ordinary skill in the art would have been motivated to make such a modification since it would have been obvious to try, as there are a limited number of memory types for storing data and the use of DRAM and SRAM is well-known in the art, as taught by GUENTHER. NICOL and GUENTHER are analogous/in the same field of endeavor as both references are directed to processing systems and memory.
17. The processor of claim 1 (see NICOL above), wherein the plurality of memory units comprise dynamic random access memory (DRAM) (see GUENTHER below).
GUENTHER discloses the following limitations that are not disclosed by NICOL: wherein the plurality of memory units comprise dynamic random access memory (DRAM) (see [0024]: use of DRAM or SRAM for data and instruction memories). The use of DRAM and SRAM for storing data to be used by a processor is well-know and common in the art. There are a limited number of memory types that can be used for storing data. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify NICOL to use DRAM memory units, as disclosed by GUENTHER. One of ordinary skill in the art would have been motivated to make such a modification since it would have been obvious to try, as there are a limited number of memory types for storing data and the use of DRAM and SRAM is well-known in the art, as taught by GUENTHER. NICOL and GUENTHER are analogous/in the same field of endeavor as both references are directed to processing systems and memory.
Allowable Subject Matter
Claim 20 is allowed.
Claims 8 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art generally discloses systems with arrays of processing units and memory units where instructions are assigned to an execution unit and perform operations on data in memory units.
The state of the art fails to anticipate, or render obvious, “… wherein the ICU is configured to issue the instruction to a first execution unit of the plurality of execution units, and wherein the first execution unit is configured to execute the instruction and propagate the instruction to a second execution unit of the plurality of execution units along a second direction that is perpendicular to the first direction.”
The state of the art fails to anticipate or render obvious, “… generate, based on the model, an instruction stream comprising a plurality of instructions targeting the plurality of execution units; wherein the compiler specifies by the instruction stream, for each instruction of the plurality of instructions, a time at which the instruction will be executed and an execution unit of the plurality of execution units to execute the instruction.”
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
BORKOVIC - 11,748,622 – discloses a compiler that generates instructions based on a model, the compiler can synchronize execution of the instructions and assign instructions to specific execution units, the instruction can be commanded to wait until a prior instruction is complete and instructions can be scheduled to resolve dependencies between instructions. See columns 5-7 and 10. The reference fails to disclose specifying a time at which the instruction will be executed.
BEN-AVI – 11,599,777 – discloses a compiler that can schedule a workload for an execution unit, a processing array where each portion of the array can perform a specific task, and creating a batch of tasks to schedule for execution on an execution unit. See columns 5, 6 and 22. The reference fails to disclose specifying a time at which the instruction will be executed.
DAS – 2018/0322390 – discloses multiple compute blocks and a scheduler to synchronize multiple instructions. See [0144]-[0145] The reference fails to disclose specifying a time at which the instruction will be executed.
DUNCAN – 2013/0152093 – discloses a parallel processing array, assigning tasks to be processed where the tasks include a pointer to data for use in the processing task, dynamic scheduling of tasks based on availability of processing elements, creating a thread by grouping a plurality of instructions, creating a thread group, grouping streams of work into time slice groups that share context information and executing a run list of the thread group on the assigned channel. See [0024], [0029], [0035], [0041]-[0042], [0049], [0056]-[0064] While instructions are assigned to a channel, the execution units that execute the instructions are assigned dynamically. The instructions in the time slice group are grouped so they execute together, but a time is not specified for when the instructions are executed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136