DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Examiner has considered the IDS filed 28 October 2025. However, the IDS contained Applicant/Assignee names in various citations rather than inventor names like the IDS table requests. Therefore, the Examiner corrected the Applicant/Assignee names to instead be inventor names according to the form requested by the table. The Examiner corrected the citations according to inventor names that match the cited publication numbers. Applicant should review the IDS and confirm these are indeed the intended citations.
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Objections
Claims 2, 13, 15-16 and 19-20 are objected to because of the following informalities:
Claim 2 should be amended to recite, “activate the first memory bank” for precise antecedent basis to the recitation of “a first memory bank” in claim 1.
Claim 13 should be amened to recite, “wherein
Claim 15 should be amended to recite, “wherein the second controller is further configured to closeby using a second precharge command generated internally within the memory device if the maximum threshold amount of time has elapsed” to indicate that it is the same close operation as recited in claim 14 as performed in a certain case.
Claim 16 should be amended to recite, “wherein the second controller is further configured to closeif the maximum threshold amount of time has not elapsed” to indicate that it is the same close operation as recited in claim 14 as performed in a certain case.
Claim 19 should be amended to recite, “closing” to fit with the grammatical structure of the method claim.
Claim 20 is objected to for failing to cure the deficiencies of a base claim from which it depends.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6, 8-10, 12-16 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-7, 9-13 and 18 of U.S. Patent No. US 12,393,345 B2 (‘345). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 4-7, 9-13 and 18 of ‘345 contains every element of claims 1-6, 8-10, 12-16 and 18-20 of the instant application and as such anticipates claims 1-6, 8-10, 12-16 and 18-20 of the instant application.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berq, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Instant Application
‘345
1. A memory device, comprising: a plurality of memory banks;
a controller configured to:
determine whether a first precharge command to close a first memory bank of the plurality of memory banks was issued within a maximum threshold amount of time since issuance of an activate command for activating the first memory bank; and
issue, within the memory device and based on the first precharge command being determined to not be issued within the maximum threshold amount of time, a second precharge command to close the first memory bank.
1. A system, comprising: a host device comprising a first controller; and
a memory device comprising: a plurality of memory banks configured to store data;
a second controller configured to: receive an activate command issued by the first controller to activate a first memory bank of the plurality of memory banks; activate, in response to the activate command, the first memory bank of the plurality of memory banks; and a circuit configured to:
determine whether a first precharge command to close the first memory bank has been issued by the first controller within a maximum threshold amount of time since issuance of the activate command issued by the first controller; and
internally issue, within the memory device, a second precharge command to close the first memory bank if the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller.
2. The memory device of claim 1, wherein the controller is further configured to activate the first memory based on receipt of the activate command.
1…a second controller configured to: receive an activate command issued by the first controller to activate a first memory bank of the plurality of memory banks; activate, in response to the activate command, the first memory bank of the plurality of memory banks;
3. The memory device of claim 1, wherein the controller is further configured to determine, based on the first precharge command being determined to not be issued within the maximum threshold amount of time, that a violation of the maximum threshold amount of time since issuance of the activate command has occurred.
9. The system of claim 1, wherein the second controller is further configured to provide feedback to the first controller of the host device indicating a violation that the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller [a violation of the maximum threshold amount of time since issuance of the activate command has occurred].
4. The memory device of claim 3, wherein the controller is further configured to determine a cause for the violation of the maximum threshold amount of time since issuance of the activate command.
9. The system of claim 1, wherein the second controller is further configured to provide feedback to the first controller of the host device indicating a violation that the first precharge command from the first controller has not been issued [a cause] within the maximum threshold amount of time since issuance of the activate command by the first controller.
5. The memory device of claim 4, wherein the controller is further configured to provide feedback providing an indication of the cause for the violation.
9. The system of claim 1, wherein the second controller is further configured to provide feedback to the first controller of the host device indicating a violation that the first precharge command from the first controller has not been issued [a cause] within the maximum threshold amount of time since issuance of the activate command by the first controller.
6. The memory device of claim 1, wherein the controller is further configured to close, based on the first precharge command being determined to be issued within the maximum threshold amount of time, the first memory bank in response to receiving the first precharge command.
4. The system of claim 1, wherein the second controller is further configured to: receive the first precharge command from the first controller of the host device; and close the first memory bank based on the first precharge command.
8. The memory device of claim 1, wherein the controller is further configured to return the first memory bank to an idle state after closing the first memory bank.
5. The system of claim 4, wherein the second controller is further configured to return the first memory bank to an idle state upon closing the first memory bank.
9. The memory device of claim 1, wherein the controller is further configured to receive the first precharge command from a host device.
1. A system, comprising: a host device comprising a first controller; and a memory device comprising: a plurality of memory banks configured to store data; a second controller configured to: receive an activate command issued by the first controller to activate a first memory bank of the plurality of memory banks…
10. The memory device of claim 1, wherein the controller is further configured to select the maximum threshold amount of time based on at least one characteristic of the memory device.
6. The system of claim 1, wherein the circuit is further configured to select the maximum threshold amount of time based on at least one characteristic of the memory device.
12. The memory device of claim 1, wherein the memory device further comprises a circuit configured to count pulse signals generated by an oscillator of the memory device after the activate command is issued.
10. The system of claim 1, wherein the circuit further comprises: an oscillator configured to generate periodic pulse signals; and a counter configured to increment a first count value as each of the periodic pulse signals is generated by the oscillator.
11. The system of claim 10, wherein the circuit is further configured to: trap a second count value corresponding to a pulse signal of the periodic pulse signals occurring at a time of activation of the first memory bank in accordance with the activate command issued by the first controller.
12. The system of claim 11, wherein the circuit is further configured to: add a constant associated with the maximum threshold amount of time to the second count value trapped by the circuit to generate a sum; compare the first count value to the sum; and internally issue the second precharge command to close the first memory bank if the first count value is greater than or equal to the sum.
13. The memory device of claim 1, wherein therein the controller is configured to generate a notification indicating that the maximum threshold amount of time has been exceeded if the first precharge command is determined to not be issued within the maximum threshold amount of time.
9. The system of claim 1, wherein the second controller is further configured to provide feedback to the first controller of the host device indicating a violation that the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller.
14. A system, comprising:
a host device comprising a first controller;
and a memory device comprising: at least one memory bank;
and a second controller configured to: activate, based on an activate command, a first memory bank of the at least one memory bank;
determine whether a maximum threshold amount of time has elapsed since receiving the activate command, wherein the maximum threshold amount of time is a maximum amount of time for receiving a first precharge command to close the first memory bank since receiving the activate command at the memory device; and
close the first memory bank if the maximum threshold amount of time has elapsed.
1. A system, comprising:
a host device comprising a first controller;
and a memory device comprising: a plurality of memory banks configured to store data;
a second controller configured to: receive an activate command issued by the first controller to activate a first memory bank of the plurality of memory banks; activate, in response to the activate command, the first memory bank of the plurality of memory banks; and
a circuit configured to: determine whether a first precharge command to close the first memory bank has been issued by the first controller within a maximum threshold amount of time since issuance of the activate command issued by the first controller; and internally issue, within the memory device,
a second precharge command to close the first memory bank if the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller.
15. The system of claim 14, wherein the second controller is further configured to close, if the maximum threshold amount of time has elapsed, the first memory bank using a second precharge command generated internally within the memory device.
1…and internally issue, within the memory device,
a second precharge command to close the first memory bank if the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller.
16. The system of claim 14, wherein the second controller is further configured to close, if the maximum threshold amount of time has not elapsed, the first memory bank using the first precharge command.
4. The system of claim 1, wherein the second controller is further configured to: receive the first precharge command from the first controller of the host device; and close the first memory bank based on the first precharge command.
18. The system of claim 14, wherein the second controller is further configured to identify whether a host device that issued the activate command has malfunctioned, is unavailable, has been hacked, or a combination thereof.
7. The system of claim 1, wherein the second controller is further configured to facilitate identification of a malicious attack on the memory device if the first precharge command from the first controller has not been issued within the maximum threshold amount of time since issuance of the activate command by the first controller.
19. A method, comprising:
determining, by utilizing a memory device comprising at least one memory bank, whether a maximum row active time has elapsed since receiving an activate command, wherein the maximum row active time is a maximum amount of time for receiving a first precharge command to close a first memory bank of the at least one memory bank since receiving the activate command; and
close the first memory bank using a second precharge command if the maximum row active time has elapsed since receiving the activate command.
13. A method comprising: activating, by utilizing a memory device, a first memory bank of a plurality of memory banks of the memory device based on an activate command issued by a host device;
calculating whether a maximum row active time has elapsed since receiving the activate command from the host device, wherein the maximum row active time is a maximum amount of time for receiving a first precharge command from the host device to close the first memory bank since receiving the activate command at the memory device;
closing the first memory bank if the first precharge command from the host device is received at the memory device and the maximum row active time has not elapsed; and closing the first memory bank with a second precharge command generated internally by the memory device if the maximum row active time has elapsed.
20. The method of claim 19, further comprising providing a notification to a host device indicating that the maximum row active time has elapsed.
18. The method of claim 13, further comprising providing a notification to the host device if the maximum row active time has elapsed.
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of ‘345 in view of US Patent Application Publication US 2004/0136250 A1 (Takahashi).
Instant Application
‘345
Takahashi
7. The memory device of claim 1
wherein the controller is further configured to: open, in response to the activate command, a row in the first memory bank;
and transfer a charge associated with the row to a sense amplifier to sense the charge.
Claim 1 as seen in the analysis performed above
1… a second controller configured to: receive an activate command issued by the first controller to activate a first memory bank of the plurality of memory banks; activate, in response to the activate command, the first memory bank of the plurality of memory banks;
(by teaching that a sense amplifier (13c) detects the potential of the bit lines (sense the charge) according to the row address provided by the row address signal, row control circuit, and row decoder by activating the appropriate wordline in order to read or write a row/page of the memory cell array (13) of an SDRAM memory cell array in response to an activate command [0029-0034] [Fig. 3A]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified activating the memory bank as taught by ‘345 to include activating the corresponding wordline corresponding to the address provided as part of the activate command and sensing the charge of the memory cells by sensing the bit lines with a sense amplifier as taught by Takahashi.
One of ordinary skill in the art would have been motivated to make this modification because it would have only required the combination of known elements according to known methods to yield predictable results. ‘345 teaches to activate a bank of memory in response to an activate command without teaching a specific mechanism for accomplishing the result and Takahashi teaches a specific mechanism that can be used to accomplish the result by teaching the sense amplifier with the row control circuit and row decoder that are used together to activate the corresponding wordline and detect the potential of the bit lines in order to obtain the data stored within the DRAM memory cell array in response to an activate command as taught by Takahashi. One of ordinary skill in the art could have combined the mechanism for activating the word line and obtaining a row/page of data in response to an activate command as taught by Takahashi to implement the function of activating a memory bank as taught by Bacchus according to known methods and the results would have been predictable. Furthermore, in combination, each element would continue to perform the same function that it did separately.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11 and 17-18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 11:
Claim 11 recites detecting “a leaking charge from at least one memory cell of the first memory bank as a cause for a violation of the maximum threshold amount of time”. The specification, however, describes leakage as a potential effect or consequence of a memory bank remaining open too long, not as the cause of the failure to timely issue a precharge command. Although [0049] states that leakage may be detected when determining the cause of the violation, the disclosed causes are, for example, hacking or host malfunction that prevents issuance of the precharge command. However, at most, detected leakage is evidence of the occurrence or consequence of the violation, not evidence of its cause. Therefore, the disclosure does not reasonably convey possession of using detecting a leakage of charge from a memory cell itself as the cause of the maximum threshold time violation as claimed.
Regarding claim 17:
Claim 17 requires the second controller to determine whether the issuance of the first precharge command was prevented. “An original claim may lack written description support when (1) the claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved” [MPEP 2163.03(V)]. Although [0049] discloses that “the system 100, such as via the memory device or other device” may determine that a hacker prevented issuance of a precharge command, the disclosure does not attribute that determination specifically to the second controller. Instead, [0049] states more generally that identification of the cause may be “performed and/or facilitated” using various components of the system. Therefore, the disclosure contemplates a determination made through coordination among multiple elements, or by elements other than the controller itself, rather than possession of the second controller independently performing the claimed determination. Furthermore, the specification may disclose detecting that the expected precharge command was not received, but it does not reasonably convey possession of the second controller determining that the issuance was affirmatively prevented. Failure to receive the command does not, by itself, establish why the host did not issue it. The disclosure identifies the diagnostic conclusions to be reached but provides little or no technical teaching connecting the information available to the second controller with those conclusions. In other words, it describes the desired result without adequately describing the diagnostic mechanism by which the controller obtains and distinguishes the information necessary to reach the claimed result (determine the host is prevented from sending the precharge command). Accordingly, the disclosure does not reasonably convey possession of the claimed functionality.
Regarding claim 18:
Claim 18 requires the second controller to identify whether the host device has malfunctioned, is unavailable, has been hacked, or a combination thereof. “An original claim may lack written description support when (1) the claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved” [MPEP 2163.03(V)]. Paragraph [0049] discloses these conditions only at the system or memory-level and describes identification of the cause as potentially relying on information or actions external to the controller. For example, [0049] states that the memory device may receive a notification from the host device itself identifying the cause, may transmit a signal to ping the host device and determine that no response is received, and may perform other actions to facilitate identification. Paragraph [0049] states more generally that identification of the cause may be “performed and/or facilitated” using various components of the system. Therefore, the disclosure contemplates a determination made through coordination among multiple elements, or by elements other than the controller itself, rather than possession of the second controller independently performing the claimed determination. Furthermore, the specification discloses mechanisms by which the memory device or memory system may infer or receive information concerning the host but does not disclose that the second controller itself possesses or independently obtains the information necessary to perform the claimed determination. Additionally, the specification lists several possible causes of the same observable condition but does not disclose a reliable basis by which the second controller distinguishes among those causes. Therefore, the disclose appears to state the desired diagnostic result rather than teach the claimed diagnostic functionality. Accordingly, the specification does not reasonably convey possession of the controller being able to make determinations about the host system that are external to the second controller.
Claims 11 and 17-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Regarding claim 11:
Considering the Wands factors:
The breadth of the claims: claim 11 broadly encompasses detecting leakage as a cause of the timing violation without specifying any leakage threshold, sensing mechanism, or causal criteria.
The nature of the invention: the claimed functionality requires correlating a physical memory cell condition (leakage) with the cause of a command level timing violation. However, there is no disclosed probabilistic or definite causal relationship between cell leakage and a specific cause of a timing violation. For example, the specification discloses multiple causes for the timing violation, including hacking, host malfunction, unavailability, or other failure to issue the precharge command. Detection of leakage may indicate that the memory bank remained active too long but does not make any one of these disclosed causes more likely than another. Therefore, determining from leakage which condition caused the violation is a diagnostic determination that is not predictable and would require further characterization, correlation, or research not provided by the specification.
The state of the prior art: even assuming techniques for detecting memory-cell leakage were known, the record does not establish that determining such leakage to be the cause of failure to timely receive a precharge command was conventional.
The level of one of ordinary skill: a high level of skill in memory-device design does not supply the omitted causal relationship.
The level of predictability in the art: detecting leakage does not predictably explain why a precharge command was not received timely, particularly where the specification describes leakage as a consequence of an extended row-active time.
The amount of direction provided by the inventor: the specification merely states that leakage may be detected without explaining how leakage is attributed to a cause of the violation.
The existence of working examples: no example demonstrates the causal determination from leakage detection claimed.
The quantity of experimentation needed to make or use the invention based on the content of the disclosure: a skilled artisan would be required to develop the sensing and diagnostic criteria to distinguish leakage as a cause from leakage occurring as a consequence of the violation, as well as correlate the nature/pattern/profile/fingerprint of the leakage to specific causes.
Taken together, based on the evidence regarding each of the above factors, the specification, at the time the application was filed, would not have taught one skilled in the art how to make and/or use the full scope of the claimed invention without undue experimentation.
Regarding claim 17:
The specification does not enable the full scope of “wherein the second controller is further configured to determine whether the first precharge command was prevented from being issued” without undue experimentation.
Considering the Wands factors:
The breadth of the claims: the claim encompasses any many in which issuance from the host may be prevented.
The nature of the invention: the claimed determination concerns forming knowledge about an event that occurs externally to the second controller, rather than merely non-receipt of the precharge command.
The state of the prior art: the record does not establish that determining the affirmative prevention of issuance of a command from an external memory controller is conventional in the art.
The level of one of ordinary skill: although skilled artisans would understand memory controllers, such knowledge would not supply information regarding the full scope of host-side events that could cause non-receipt of a command (hacking, malfunction, power-loss, breakdown of the signal path from the host to the memory controller or any other undisclosed and uncontemplated reason).
The level of predictability in the art: non-receipt of a precharge command does not predictably establish that its issuance was prevented.
The amount of direction provided by the inventor: [0049] identifies possible causes and components that may facilitate detection, but does not explain how the second controller by itself would determine that issuance was prevented.
The existence of working examples: there are no examples of the second controller determining prevention.
The quantity of experimentation needed to make or use the invention based on the content of the disclosure: a skilled artisan would need to develop and characterize additional inputs and diagnostic criteria to distinguish prevention from any other conceivable cause of non-receipt. Accordingly, the required experimentation would be undue.
Taken together, based on the evidence regarding each of the above factors, the specification, at the time the application was filed, would not have taught one skilled in the art how to make and/or use the full scope of the claimed invention without undue experimentation.
Regarding claim 18:
The specification does not enable the full scope of “wherein the second controller is further configured to identify whether a host device that issued the activate command has malfunction, is unavailable, has been hacked, or a combination thereof” without undue experimentation.
Considering the Wands factors:
The breadth of the claims: the claim multiple distinct host conditions that are external to the second controller and without limiting how they are identified or manifest themselves in the host. For example, “has been hacked” includes any conceivable method of hacking and not merely the attacks that interfere with the issuance of the precharge command as disclosed.
The nature of the invention: the controller must diagnose multiple external host conditions that may produce the same observable failure to issue a precharge command, or may exhibit behavior that is not even observable to the second controller at all (for example, if the host was hacked in a way where the attacker is merely monitoring the system rather than tampering with issuance of the precharge commands or any commands issued to the second controller).
The state of the prior art: the record does not establish that distinguishing these conditions from the disclosed information was conventional.
The level of one of ordinary skill: although skilled artisans would understand memory controllers, such knowledge would not supply information regarding the full scope of host-side conditions that would allow detection of any conceivable state of the host that results in the host being malfunctioned, unavailable, or in the state of having been hacked, or a combination thereof.
The level of predictability in the art: the disclosed observations such as nonresponse, leakage, or changed data to not uniquely or reliably distinguish among malfunction, unavailability, or hacking. Furthermore, hacking may be intentionally concealed and therefore may not produce a unique or readily observable indication available to the second controller or any other component of the system. The disclosed techniques in [0049] involving coordination among the system components may be useful in detecting a particular attack or malfunction that manifests through memory-command behavior, but the claim broadly encompasses a host that “has been hacked” including attacks that may produce no observable indication at the second controller. The claim is therefore not predictable across its full scope as there is not a predictable way to detect any conceivable method of hacking, malfunction, or unavailability of a host at an external second controller.
The amount of direction provided by the inventor: [0049] identifies possible causes and components that may facilitate detection but provides no criteria for distinguishing among the claimed conditions. Furthermore, the disclosure is only relevant to hacking, malfunctions, or unavailability of the host that may result in timing violations or non-issuance of a precharge command, but do not relate to the full scope of any conceivable method or state of the host of having been hacked, malfunctioned, or unavailable allowed by the claims.
The existence of working examples: there are no examples of the second controller determining prevention.
The quantity of experimentation needed to make or use the invention based on the content of the disclosure: a skilled artisan would need to develop and characterize the inputs, correlations, and decision criteria necessary to identify any conceivable way a host could have been hacked, malfunctioned, or unavailable.
Taken together, based on the evidence regarding each of the above factors, the specification, at the time the application was filed, would not have taught one skilled in the art how to make and/or use the full scope of the claimed invention without undue experimentation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, 14-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication US 2018/0293189 A1 (Bacchus) in view of US Patent Application Publication US 2004/0136250 A1 (Takahashi) in further view of US Patent Application Publication US 2003/0081483 A1 (De Paor).
Regarding claim 1 and analogous claims 14-15 and 19:
Bacchus discloses:
A memory device comprising (memory device (100)/(204) having memory storage media (110) and a memory manager [Fig. 1] [0010-0012]).
a memory bank (memory storage media includes a bank of memory as the buffer may be a row buffer (130) for a bank (110) of synchronous DRAM memory [0001] [Fig. 1] [0012]).
a controller configured to: (memory manager (120)/(220) controls externally input commands from command/address bus of the memory controller (208) and also autonomous operations of the memory device and may be implemented as a state machine, gate array, processor, or other circuitry, and includes a command and address decoder (250) (270) as well as a timing circuit (260) and counter (262) [0011] [0014] [0020-0022])
determine whether a first precharge command to close a first memory bank was issued (by teaching that the command decoder determines whether a command received on the command/address bus from the external memory controller is an explicit precharge command, and if so, the memory manager (120) may transfer the contents of the buffer (130) to the bank of the memory storage media (110) [0016-0017] [0021] [Fig. 1]).
within a maximum threshold amount of time since issuance of any command including an activate command for activating the first memory bank (by teaching timing the amount of time after a page has been activated (with an internal or explicit activate command) [0008] [0016-0017]. The elapsed time after the page has been activated is tracked, and the memory manager determines whether the elapsed time reaches a predetermined threshold [0022] [0029]. This time may be the time since the activate command is issued, but the timer may be reset by any explicit command received on the command/address bus [0022] [0029]. The timer may track whether the precharge command is issued within this maximum time [0022-0029] [Fig. 4]).
and issue, within the memory device and based on the first precharge command being determined to not be issued within the maximum threshold amount of time a second precharge command to close the first memory bank (the decoder can identify an explicit precharge command, which may reset the timer [0016-0017] [0022] [0029]. However, if the timer reaches the threshold value before the explicit precharge command is reached, then the memory manager (220) performs an autonomous precharge (second precharge command issued within the memory device) [0029] [Fig. 4]. Where the autonomous precharge closes the currently active page by writing the contents of the row buffer back (130)/(230) to the bank of the memory storage media (110)/(210) [0008] [0012] [0022] [0029] [0034]).
Bacchus does not explicitly disclose, but Takahashi teaches:
to issue an internal precharge command if precharge is not performed within a maximum threshold amount of time since issuance of an activate command for activating the first memory bank (by teaching that after the activate command signal is received, the time before a next precharge may be very long. In this case, if a wordline is left in the selected state for a long time, the transistor deteriorates, and the reliability of the memory device is lowered. Therefore, a maximum time limit is set for the length of time for which a wordline may remain selected after an activate command [0042-0043]. More specifically, a counter may begin counting when an ACT command is output from the command buffer circuit (12), and if the counter reaches a preset value before a precharge is performed, an internal precharge command is issued [0046-0048]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified memory manager as taught by Bacchus to additionally include counting the time since a last activate command was issued and issuing an internal precharge command when the counter value reaches a preset value as taught by Takahashi.
One of ordinary skill in the art would have been motivated to make this modification because if a wordline remains selected for too long, the transistor deteriorates, and the reliability of the memory device is lowered as taught by Takahashi in [0042].
Bacchus does not explicitly disclose, but De Paor teaches:
to arrange the DRAM memory device into a plurality of memory banks such that the first memory bank is a first memory bank among the plurality of memory banks (by teaching that synchronous DRAMs are usually organized into several banks, typically four [0001]. Arranging the memory into banks enables more efficient access because one bank can be prepared for access while another bank is undergoing access [0002]. In this way, operations on one bank may be run in parallel with operations on another [0010] [0013]. A bank is opened with an active command that opens a row to make read for a data operation and is closed with a precharge command to close the row again [0013]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified precharging method applied to a memory bank of the memory device as taught by Bacchus to be applied to a plurality of banks and have the memory device include a plurality of memory banks as taught by Takahashi.
One of ordinary skill in the art would have been motivated to make this modification because arranging the memory into a plurality of banks makes for more efficient access and allows operations to be run in parallel on multiple banks as taught by De Paor in [0002] [0010] [0013].
Regarding claim 2:
The memory device of claim 1 is made obvious by Bacchus in view of Takahashi in further view of De Paor (Bacchus-Takahashi-DePaor).
Bacchus further discloses:
wherein the controller is further configured to activate the first memory based on receipt of the activate command (by teaching that when a memory page of a bank of memory has been activated, the memory manager of the memory device begins tracking an amount of time since a last access of the memory device. The memory page of the bank may be activated with an explicit activate command (based on receipt of the activate command) [0008] [0016-0017] [0022] [0029]).
Regarding claim 3:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
wherein the controller is further configured to determine, based on the first command being determined to not be issued within the maximum threshold amount of time, that a violation of the maximum threshold amount of time (by teaching that the decoder can identify an explicit precharge command, which may reset the timer [0016-0017] [0022] [0029]. However, if the timer reaches the threshold value before the explicit precharge command is reached (i.e., a violation of the maximum threshold amount of time), then the memory manager (220) performs an autonomous precharge (second precharge command issued within the memory device) [0029] [Fig. 4]. Where the autonomous precharge closes the currently active page by writing the contents of the row buffer back (130)/(230) to the bank of the memory storage media (110)/(210) [0008] [0012] [0022] [0029] [0034]).
Bacchus does not explicitly disclose, but Takahashi teaches:
since issuance of the activate command has occurred (by teaching that after the activate command signal is received, the time before a next precharge may be very long. In this case, if a wordline is left in the selected state for a long time, the transistor deteriorates, and the reliability of the memory device is lowered. Therefore, a maximum time limit is set for the length of time for which a wordline may remain selected after an activate command [0042-0043]. More specifically, a counter may begin counting when an ACT command is output from the command buffer circuit (12), and if the counter reaches a preset value before a precharge is performed, an internal precharge command is issued [0046-0048]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified memory manager as taught by Bacchus to additionally include counting the time since a last activate command was issued and issuing an internal precharge command when the counter value reaches a preset value as taught by Takahashi.
One of ordinary skill in the art would have been motivated to make this modification because if a wordline remains selected for too long, the transistor deteriorates, and the reliability of the memory device is lowered as taught by Takahashi in [0042].
Regarding claim 4:
The memory device of claim 3 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
Bacchus further discloses, wherein the controller is further configured to determine a cause for the violation of the maximum threshold amount of time (by teaching that the decoder can identify an explicit precharge command, which may reset the timer [0016-0017] [0022] [0029]. However, if the timer reaches the threshold value before the explicit precharge command is reached (a cause for the violation of the maximum threshold amount of time – i.e., the explicit precharge command is not received), then the memory manager (220) performs an autonomous precharge (second precharge command issued within the memory device) [0029] [Fig. 4]. Where the autonomous precharge closes the currently active page by writing the contents of the row buffer back (130)/(230) to the bank of the memory storage media (110)/(210) [0008] [0012] [0022] [0029] [0034]).
Bacchus does not explicitly disclose, but Takahashi teaches:
since issuance of the activate command (by teaching that after the activate command signal is received, the time before a next precharge may be very long. In this case, if a wordline is left in the selected state for a long time, the transistor deteriorates, and the reliability of the memory device is lowered. Therefore, a maximum time limit is set for the length of time for which a wordline may remain selected after an activate command [0042-0043]. More specifically, a counter may begin counting when an ACT command is output from the command buffer circuit (12), and if the counter reaches a preset value before a precharge is performed, an internal precharge command is issued [0046-0048]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified memory manager as taught by Bacchus to additionally include counting the time since a last activate command was issued and issuing an internal precharge command when the counter value reaches a preset value as taught by Takahashi.
One of ordinary skill in the art would have been motivated to make this modification because if a wordline remains selected for too long, the transistor deteriorates, and the reliability of the memory device is lowered as taught by Takahashi in [0042].
Regarding claim 6 and analogous claim 16:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
wherein the controller is further configured to close, based on the first precharge command being determined to be issued within the maximum threshold amount of time, the first memory bank in response to receiving the first precharge command (by teaching receiving an explicit precharge command through the command/address interface, decoding the command, and when it is issued, transferring the row buffer contents for the bank back to the memory storage media. The memory manager tracks whether precharge occurs before the timer reaches its threshold, if the explicit precharge is received before the timer reaches the threshold, then the memory bank is closed by transferring the row buffer contents for the bank to the memory storage media [0012] [0016-0017] [0021-0022] [0029])
Regarding claim 7:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
wherein the controller is further configured to: open, in response to the activate command, a row in the first memory bank (by teaching activating a page/row of the bank by transferring it from the storage media to the row buffer in response to activation. The relevant row/page of a bank may be opened by the explicit activate command [0008] [0012-0013] [0016-0017].
Bacchus does not explicitly disclose, but Takahashi teaches:
and transfer a charge associated with the row to a sense amplifier to sense the charge (by teaching that a sense amplifier (13c) detects the potential of the bit lines (sense the charge) according to the row address provided by the row address signal, row control circuit, and row decoder by activating the appropriate wordline in order to read or write a row/page of the memory cell array (13) of an SDRAM memory cell array in response to an activate command [0029-0034] [Fig. 3A]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transferring of the data from the DRAM storage media to the row buffer in response to the activate command as taught by Bacchus to include activating the corresponding wordline corresponding to the address provided as part of the activate command and sensing the charge of the memory cells by sensing the bit lines with a sense amplifier as taught by Takahashi.
One of ordinary skill in the art would have been motivated to make this modification because it would have only required the combination of known elements according to known methods to yield predictable results. Bacchus teaches to obtain the row/page of data from the DRAM storage media and place it into the row buffer in response to an activate command without teaching a specific mechanism for accomplishing the result and Takahashi teaches a specific mechanism that can be used to accomplish the result by teaching the sense amplifier with the row control circuit and row decoder that are used together to activate the corresponding wordline and detect the potential of the bit lines in order to obtain the data stored within the DRAM memory cell array in response to an activate command as taught by Takahashi. One of ordinary skill in the art could have combined the mechanism for obtaining a row/page of data as taught by Takahashi to implement the function of obtaining the row/page of data and playing it in the row buffer as taught by Bacchus according to known methods and the results would have been predictable, the row/page of data stored in the memory cells of the DRAM memory cell array would be obtained. Furthermore, in combination, each element would continue to perform the same function that it did separately.
Regarding claim 8:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
wherein the controller is further configured to return the first memory bank to an idle state after closing the first memory bank (by teaching closing the active page by precharging it and returning the row-buffer contents to the bank of the memory storage media [0008] [0012] [0022] [0029]. After the bank is precharged/closed, the memory manager and storage media may enter a low-power (idle) state by performing self-refresh, which conserves overall system power. The memory storage media cannot respond to another access request (i.e., is idle) unless another activate command is performed to open a page/row of the memory storage media [0029-0030] [0032-0033].
Regarding claim 9:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
wherein the controller is further configured to receive the first precharge command from a host device (by disclosing that the memory device (104/204) including the memory manager (220) (memory controller) receives the explicit precharge command over the command/address bus through input (140/240) from the external memory controller (208), which may be a processor (host) [0016] [0020]).
Claims 5, 10, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bacchus-Takahashi-DePaor in further view of US Patent Application Publication US 2016/0070483 A1 (Yoon).
Regarding claim 5:
The memory device of claim 4 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus does not explicitly disclose, but Yoon teaches:
wherein the controller is further configured to provide feedback providing an indication of the cause for the violation (by teaching a device-side memory controller providing feedback information to a host-side memory controller in response to commands not meeting specified timing parameters, because commands need to meet specified timing parameters [0008] [0017-0018]. The feedback can identify the latency currently experienced by the device-side controller [0019]. The activate (ACT) and precharge (PRE) commands may be the commands that experience the longer than expected latencies that are notified to the host-side controller using feedback information when there is a deviation from the usual latency [0033-0036]. The feedback information can include information about the experienced latency, such as an amount of time or whether it is greater than usual latency information, and status information relating to the non-deterministic access commands [0039] [0048-0050]. In response to the feedback information, the host can make scheduling decisions as appropriate [0050]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device controller determining that an explicit recharge command has not been received within a threshold amount of time as taught by Bacchu to include providing feedback to the host indicating the experienced latency of the precharge command and status information relating to the late arriving precharge command as taught by Yoon.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the host-side memory controller to make scheduling decisions as appropriate to resolve the unusual latency of the precharge command as taught by Yoon.
Regarding claim 13 and analogous claim 20:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus does not explicitly disclose, but Yoon teaches:
wherein therein the controller is configured to generate a notification indicating that the maximum threshold amount of time has been exceeded if the first precharge command is determined to not be issued within the maximum threshold amount of time (by teaching a device-side memory controller providing feedback information to a host-side memory controller in response to commands not meeting specified timing parameters, because commands need to meet specified timing parameters [0008] [0017-0018]. The feedback can identify the latency currently experienced by the device-side controller [0019]. The activate (ACT) and precharge (PRE) commands may be the commands that experience the longer than expected latencies that are notified to the host-side controller using feedback information when there is a deviation from the usual latency [0033-0036]. The feedback information can include information about the experienced latency, such as an amount of time or whether it is greater than usual latency information, and status information relating to the non-deterministic access commands [0039] [0048-0050]. In response to the feedback information, the host can make scheduling decisions as appropriate [0050]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device controller determining that an explicit recharge command has not been received within a threshold amount of time as taught by Bacchu to include providing feedback to the host indicating the experienced latency of the precharge command and status information relating to the late arriving precharge command as taught by Yoon.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the host-side memory controller to make scheduling decisions as appropriate to resolve the unusual latency of the precharge command as taught by Yoon.
Regarding claim 10:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus does not explicitly disclose, but wherein the controller is further configured to select the maximum threshold amount of time based on at least one characteristic of the memory device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Bacchus-Takahashi-DePaor in further view of US Patent Application Publication US 2022/0165347 A1 (Pan).
Regarding claim 12:
The memory device of claim 1 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus further discloses:
wherein the memory device further comprises a circuit configured to count the amount of time after the activate command is issued (by teaching a counter of the timing circuit (260) to count the time via a clock after an activate command is issued and the row/page is opened [0021-0022]).
Bacchus does not explicitly disclose, but Pan teaches:
that a timer circuit may be configured to count pulse signals generated by an oscillator of the memory device (by teaching that a timer circuit (458) that is used to measure a period of time that a word line is activated, for example, in response to an ACT signal, may include an oscillator and a pulse generator. The timer circuit may be a multibit counter and count the number of oscillations and then generate a pulse whenever the multibit counter reaches a maximum count value and then may be reset. The pulse values may be counted by a count update circuit (456) to keep track of the amount of time that a word line is active in order to determine the amount of time the word line is activated [0068-0072]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the counter keeping track of how long the row/page is opened according to a clock signal as taught by Bacchus to be performed by the timer circuit including an oscillator that generates pulses when a multi-bit counter reaches a maximum threshold value, where the pulses may be counted by a count update circuit in order to track the amount of time a word line (i.e., row/page) is active (i.e., opened) as taught by Pan because it would have only required the combination of known elements according to known methods to yield predictable results. Particularly, Bacchus teaches counting the clock signal to keep track of how long a row/page is active/open but does not teach how the clock signal is generated. Pan teaches that the clock signal may be generated by outputting a pulse whenever a multi-bit counter counts a maximum threshold number of oscillations of the oscillator, which may be counted to keep track of the duration of how long a wordline (i.e., row/page) is activated (i.e., open). Accordingly, one of ordinary skill in the art could have combined the use of the clock signal taught by Bacchus by generating it with the circuit including the oscillator and multi-bit counter taught by Pan according to known methods and the results would have been predictable. Furthermore, in combination, each element would continue to perform the same function that it did separately.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bacchus-Takahashi-DePaor in further view of US Patent Application Publication US 2015/0121133 A1 (Wang).
Regarding claim 17:
The system of claim 14 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus does not explicitly disclose, but Wang teaches:
wherein the second controller (a memory interface/buffer circuit positioned between the host memory controller and the memory devices. The host issues commands to the memory interface circuit, which checks the commands with a protocol checker before forwarding them to the DRAM [0022] [0044] [Fig. 4])
is further configured to determine whether the first precharge command was prevented from being issued (the host memory controller issues commands to the memory interface circuit [0039-0040]. The commands are monitored by the protocol checker of the interface circuit, and include commands such as a row activation command [0043] [Fig. 4] the protocol checker (600) of the interface circuit (510) examines host commands/control signals against command history (612), current memory bank states (611), and elapsed timing compared to timing parameters stored in a table (620) [0043]. The protocol checker does this to identify faults and/or failures [0044] and uses its state machine for failure detection [0046] [Fig. 4] [Fig. 5]. If a fault and/or failure is detected because the command violates the protocol, such as a precharge command [0033-0034] [0043] [0048] [Fig. 3B], the received command is not forwarded (prevented from being issued) to the DRAM [0040-0041]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory manager as taught by Bacchus to include the protocol checker for detecting and identifying faults and/or failures of the host memory controller and to prevent issuance of commands such as a precharge command if it violates a timing requirement of the protocol as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because it allows the memory system to detect random or erroneous commands from a catastrophic host failure, making state recovery possible and preventing the propagation of erroneous commands that may transition the memory devices to an unknown or undefined state as taught by Wang in [0024-0025] [0040-0041].
Regarding claim 18:
The system of claim 14 is made obvious by Bacchus-Takahashi-DePaor.
Bacchus does not explicitly disclose, but Wang teaches:
wherein the second controller (wang discloses a memory interface/buffer circuit position between the host memory controller and the memory devices. The host issues commands to the memory interface circuit, which checks the commands with a protocol checker before forwarding them to the DRAM [0022] [0044] [Fig. 4])
is further configured to identify whether a host device that issued the activate command (the host memory controller issues commands to the memory interface circuit [0039-0040]. The commands are monitored by the protocol checker of the interface circuit, and include commands such as a row activation command [0043] [Fig. 4])
has malfunctioned, is unavailable, has been hacked, or a combination thereof (the protocol checker (600) of the interface circuit (510) examines host commands/control signals against command history (612), current memory bank states (611), and elapsed timing compared to timing parameters stored in a table (620) [0043]. The protocol checker does this to identify faults and/or failures [0044] and uses its state machine for failure detection [0046] [Fig. 4] [Fig. 5]. If a fault and/or failure is detected because the command violates the protocol (i.e., the host malfunctioned by sending a command that violates the protocol), the received command is not forwarded to the DRAM [0040-0041]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory manager as taught by Bacchus to include the protocol checker for detecting and identifying faults and/or failures of the host memory controller (i.e., malfunction of the host) as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because it allows the memory system to detect random or erroneous commands from a catastrophic host failure, making state recovery possible and preventing the propagation of erroneous commands that may transition the memory devices to an unknown or undefined state as taught by Wang in [0024-0025] [0040-0041].
Subject Matter Free From Prior Art
Claim 11 is not rejected with prior art. However, the claim is rejected under 35 USC §112(a) and accordingly, is not indicated as allowable.
Regarding claim 11, US Patent Application Publication US 2022/0284944 A1 (Benedict) – teaches monitoring cell leakage in memory cells of a DRAM memory array to detect possible row-hammer attacks [0012] [0014] [0024] [0031] [0036]. This leakage is indicative of disturbance, potentially from activation of neighboring word lines (such as during a row-hammer attack). However, detection of this leakage does not affirmatively establish that the leaking is the cause of a timer reaching a threshold after issuance of an activation command because a precharge command was not issued. Instead, it would appear to merely be evidence that a row has been activated for a long time (i.e., and not the cause of the non-reception of the precharge command). Furthermore, the prior art does not provide a reason to modify the other art of record to arrive at the invention as claimed.
Conclusion
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
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